C8051F330DR Silicon Labs, C8051F330DR Datasheet - Page 150

• Manufacturer Part Number: C8051F330DR
• Description: 8-bit Microcontrollers - MCU 8kB 10ADC
• Manufacturer: Silicon Labs

Specifications of C8051F330DR

• Product Category: 8-bit Microcontrollers - MCU
• Core: 8051
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 25 MHz
• Program Memory Size: 8 KB
• Data Ram Size: 768 B
• On-chip Adc: No
• Operating Supply Voltage: 2.7 V to 3.6 V
• Package / Case: QFN-20
• Mounting Style: SMD/SMT
• Data Rom Size: 128 B
• Interface Type: I2C, SPI, UART
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 17
• Number Of Timers: 4
• On-chip Dac: No
• Processor Series: C8051
• Program Memory Type: Flash
• Factory Pack Quantity: 1500
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 2.7 V

C8051F330/1/2/3/4/5
16.1. Enhanced Baud Rate Generation
The UART0 baud rate is generated by Timer 1 in 8-bit auto-reload mode. The TX clock is generated by
TL1; the RX clock is generated by a copy of TL1 (shown as RX Timer in Figure 16.2), which is not user-
accessible. Both TX and RX Timer overflows are divided by two to generate the TX and RX baud rates.
The RX Timer runs when Timer 1 is enabled, and uses the same reload value (TH1). However, an
RX Timer reload is forced when a START condition is detected on the RX pin. This allows a receive to
begin any time a START is detected, independent of the TX Timer state.
Timer 1 should be configured for Mode 2, 8-bit auto-reload (see
ter/Timer with Auto-Reload” on page 179
occur at two times the desired UART baud rate frequency. Note that Timer 1 may be clocked by one of six
sources: SYSCLK, SYSCLK / 4, SYSCLK / 12, SYSCLK / 48, the external oscillator clock / 8, or an exter-
nal input T1. For any given Timer 1 clock source, the UART0 baud rate is determined by Equation 16.1-A
and Equation 16.1-B.
Where T1
value). Timer 1 clock frequency is selected as described in
reference for typical baud rates and system clock frequencies is given in Table 16.1 through Table 16.6.
Note that the internal oscillator may still generate the system clock when the external oscillator is driving
Timer 1.
154
CLK
is the frequency of the clock supplied to Timer 1, and T1H is the high byte of Timer 1 (reload
Detected
Start
A)
B)
Figure 16.2. UART0 Baud Rate Logic
UartBaudRate
T1_Overflow_Rate
RX Timer
Equation 16.1. UART0 Baud Rate
Timer 1
TH1
TL1
). The Timer 1 reload value should be set so that overflows will
=
Overflow
Overflow
Rev. 1.7
1
-- -
2

=
T1_Overflow_Rate
------------------------- -
256 TH1
T1
–
Section “18. Timers” on page 177
CLK
2
2
Section “18.1.3. Mode 2: 8-bit Coun-
UART
RX Clock
TX Clock
. A quick