C8051F330DR Silicon Labs, C8051F330DR Datasheet - Page 83

• Manufacturer Part Number: C8051F330DR
• Description: 8-bit Microcontrollers - MCU 8kB 10ADC
• Manufacturer: Silicon Labs

Specifications of C8051F330DR

• Product Category: 8-bit Microcontrollers - MCU
• Core: 8051
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 25 MHz
• Program Memory Size: 8 KB
• Data Ram Size: 768 B
• On-chip Adc: No
• Operating Supply Voltage: 2.7 V to 3.6 V
• Package / Case: QFN-20
• Mounting Style: SMD/SMT
• Data Rom Size: 128 B
• Interface Type: I2C, SPI, UART
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 17
• Number Of Timers: 4
• On-chip Dac: No
• Processor Series: C8051
• Program Memory Type: Flash
• Factory Pack Quantity: 1500
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 2.7 V

C8051F330/1/2/3/4/5
EA = 0; // this is a dummy instruction with two-byte opcode.
; in assembly:
CLR EA ; clear EA bit.
CLR EA ; this is a dummy instruction with two-byte opcode.
If an interrupt is posted during the execution phase of a "CLR EA" opcode (or any instruction which clears
the EA bit), and the instruction is followed by a single-cycle instruction, the interrupt may be taken. How-
ever, a read of the EA bit will return a '0' inside the interrupt service routine. When the "CLR EA" opcode is
followed by a multi-cycle instruction, the interrupt will not be taken.
Some interrupt-pending flags are automatically cleared by the hardware when the CPU vectors to the ISR.
However, most are not cleared by the hardware and must be cleared by software before returning from the
ISR. If an interrupt-pending flag remains set after the CPU completes the return-from-interrupt (RETI)
instruction, a new interrupt request will be generated immediately and the CPU will re-enter the ISR after
the completion of the next instruction.
9.3.1. MCU Interrupt Sources and Vectors
The MCUs support 13 interrupt sources. Software can simulate an interrupt by setting any interrupt-pend-
ing flag to logic 1. If interrupts are enabled for the flag, an interrupt request will be generated and the CPU
will vector to the ISR address associated with the interrupt-pending flag. MCU interrupt sources, associ-
ated vector addresses, priority order and control bits are summarized in Table 9.4 on page 88. Refer to the
datasheet section associated with a particular on-chip peripheral for information regarding valid interrupt
conditions for the peripheral and the behavior of its interrupt-pending flag(s).
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Rev. 1.7