AD9683-170EBZ Analog Devices, AD9683-170EBZ Datasheet - Page 23

• Manufacturer Part Number: AD9683-170EBZ
• Description: Data Conversion IC Development Tools
• Manufacturer: Analog Devices
• Type: ADCr
• Series: AD9683r

Specifications of AD9683-170EBZ

• Rohs: yes
• Product: Evaluation Boards
• Tool Is For Evaluation Of: AD9683-170
• Interface Type: SPI
• Operating Supply Voltage: 1.8 V
• Description/function: Evaluation board with AD9683-170
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Operating Supply Current: 135 mA
• For Use With: AD9683-170

Data Sheet
Jitter Considerations
High speed, high resolution ADCs are sensitive to the quality of
the clock input. The degradation in SNR at a given input frequency
(f
In the equation, the rms aperture jitter represents the root-mean-
square of all jitter sources, which include the clock input, the
analog input signal, and the ADC aperture jitter specification. IF
undersampling applications are particularly sensitive to jitter,
as shown in Figure 57.
Treat the clock input as an analog signal in cases where aperture
jitter may affect the dynamic range of the AD9683. Separate the
power supplies for the clock drivers from the ADC output driver
supplies to avoid modulating the clock signal with digital noise.
Low jitter, crystal controlled oscillators make the best clock sources.
If the clock is generated from another type of source (by gating,
dividing, or another method), retime it using the original clock at
the last step.
Refer to the
ADC System Performance, and the
Sampled Systems and the Effects of Clock Phase Noise and Jitter, for
more information about jitter performance as it relates to ADCs.
IN
) due to jitter (t
SNR
80
75
70
65
60
55
50
1
Figure 57. AD9683-250 SNR vs. Input Frequency and Jitter
HF
AN-501
= −10 log[(2π × f
0.05ps
0.2ps
0.5ps
1ps
1.5ps
MEASURED
J
) can be calculated by
Application Note, Aperture Uncertainty and
INPUT FREQUENCY (MHz)
10
CLOCK INPUT
CLOCK INPUT
IN
× t
JRMS
AN-756
)
2
0.1µF
+ 10
100
0.1µF
Application Note,
(
−
SNR
AD9515
Figure 56. Differential PECL RF Clock Input Circuit
LF
LVPECL
DRIVER
/
10
)
]
1000
82.5Ω
127Ω
Rev. 0 | Page 23 of 44
V
DD
127Ω
0.1µF
0.1µF
82.5Ω
POWER DISSIPATION AND STANDBY MODE
As shown in Figure 58, the power dissipated by the
proportional to its sample rate. The data in Figure 58 was taken
using the same operating conditions as those used for the Typical
Performance Characteristics section. I
summation of I
By asserting PDWN (either through the SPI port or by asserting
the PDWN pin high), the
In this state, the ADC typically dissipates about 9 mW. Asserting the
PDWN pin low returns the
Low power dissipation in power-down mode is achieved by
shutting down the reference, reference buffer, biasing networks,
and clock. Internal capacitors are discharged when entering power-
down mode and then must be recharged when returning to normal
operation. As a result, wake-up time is related to the time spent
in power-down mode, and shorter power-down cycles result in
proportionally shorter wake-up times.
When using the SPI port interface, the user can place the ADC
in power-down mode or standby mode. Standby mode allows
the user to keep the internal reference circuitry powered when
faster wake-up times are required. See the Memory Map Register
Descriptions section and the
to High Speed ADCs via SPI, for additional details.
0.5
0.4
0.3
0.2
0.1
0
40 55 70 85 100 115 130 145 160 175 190 205 220 235 250
50Ω Tx LINE
Figure 58. AD9683-250 Power vs. Encode Rate
DVDD
50Ω
ENCODE FREQUENCY (MSPS)
0.1µF
and I
I
DVDD
AD9683
RFCLK
DRVDD
I
AD9683
AVDD
ADC
AN-877
.
is placed in power-down mode.
to its normal operating mode.
TOTAL POWER
Application Note, Interfacing
DVDD
in Figure 58 is a
AD9683
AD9683
0.25
0.20
0.15
0.10
0.05
0
is