AD9683-170EBZ Analog Devices, AD9683-170EBZ Datasheet - Page 36

• Manufacturer Part Number: AD9683-170EBZ
• Description: Data Conversion IC Development Tools
• Manufacturer: Analog Devices
• Type: ADCr
• Series: AD9683r

Specifications of AD9683-170EBZ

• Rohs: yes
• Product: Evaluation Boards
• Tool Is For Evaluation Of: AD9683-170
• Interface Type: SPI
• Operating Supply Voltage: 1.8 V
• Description/function: Evaluation board with AD9683-170
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Operating Supply Current: 135 mA
• For Use With: AD9683-170

AD9683
Reg
Addr
(Hex)
0x14
0x15
0x18
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
0x20
0x21
0x3A
Reg Addr
Name
Output mode
CML output
adjust
Input span
select
User Test
Pattern 1 LSB
User Test
Pattern 1 MSB
User Test
Pattern 2 LSB
User Test
Pattern 2 MSB
User Test
Pattern 3 LSB
User Test
Pattern 3 MSB
User Test
Pattern 4 LSB
User Test
Pattern 4 MSB
PLL low encode
SYNCINB±/
SYSREF±
control
Bit 7
(MSB)
010 = {overrange||underrange, blank},
000 = {overrange||underrange, valid},
110 = {valid, overange||underrange},
(in conjunction with Address 0x72):
001 = {overrange, underrange},
101 = {underrange, overrange},
JESD204B CS bits assignment
100 = {blank, blank},
011 = {blank, valid},
111 = {valid, blank}
Bit 6
User Test Pattern 1 LSB; use in conjunction with Address 0x0D and Address 0x61
Bit 5
Bit 4
ADC
output
disable
JESD204B
realign
SYNCINB±:
0 = normal
mode,
1 = realigns
lane on
every
active
SYNCINB±
00 = for lane speeds of
01 = for lane speeds of
User Test Pattern 1 MSB
User Test Pattern 2 MSB
User Test Pattern 3 MSB
User Test Pattern 4 MSB
User Test Pattern 2 LSB
User Test Pattern 3 LSB
User Test Pattern 4 LSB
Rev. 0 | Page 36 of 44
>2 Gbps,
<2 Gbps
Main reference full-scale VREF adjustment:
Bit 3
JESD204B
realign
SYSREF±:
0 =
normal
mode,
1 =
realigns
lane on
every
active
SYSREF±
0 0000 = internal 1.75 V p-p (default),
0 1111 = internal 2.087 V p-p,
0 0001 = internal 1.772 V p-p,
1 1111 = internal 1.727 V p-p,
1 0000 = internal 1.383 V p-p
Bit 2
ADC data
invert:
0 = normal
(default),
1 =
inverted
SYSREF±
mode:
0 =
continuous
reset clock
dividers,
1 = sync
on next
SYSREF±
rising edge
only
JESD204B CML differential output drive
100 = 109% of nominal (638 mV p-p),
101 = 117% of nominal (690 mV p-p),
110 = 126% of nominal (740 mV p-p),
111 = 134% of nominal (790 mV p-p)
000 = 75% of nominal ( 438 mV p-p),
001 = 83% of nominal (488 mV p-p),
010 = 91% of nominal (538 mV p-p),
011 = nominal (default) (588 mV p-p),
…
…
level adjustment:
Bit 1
SYSREF±
enable:
0 =
disabled,
1 =
enabled
Data format select (DFS) :
01 = twos complement
00 = offset binary,
Bit 0 (LSB)
Enable
SYNCINB±
buffer:
0 = buffer
disabled,
1 = buffer
enabled
Default
0x01
0x03
0x00
0x00
0x00
Data Sheet
Notes