ADP2442-EVALZ Analog Devices, ADP2442-EVALZ Datasheet - Page 25
![no-image](/images/manufacturer_photos/0/0/56/analog_devices_sml.jpg)
ADP2442-EVALZ
Manufacturer Part Number
ADP2442-EVALZ
Description
Power Management IC Development Tools Eval board
Manufacturer
Analog Devices
Type
DC/DC Converters, Regulators & Controllersr
Series
ADP2442r
Datasheet
1.ADP2442-EVALZ.pdf
(36 pages)
Specifications of ADP2442-EVALZ
Rohs
yes
Tool Is For Evaluation Of
ADP2442
Factory Pack Quantity
1
Data Sheet
In this example, the values listed in Table 12 are substituted for
the variables in Equation 12 and Equation 13.
Table 12. Requirements
Parameter
Ripple Current
Voltage Ripple
Voltage Droop Due
ESR
f
The calculation based on the output voltage ripple (see
Equation 12) dictates that the minimum output capacitance is
Whereas the calculation based on the transient load (see
Equation 13) dictates that the minimum output capacitance is
To meet both requirements, use the value determined by the
latter equation. As shown in Figure 60, capacitance degrades
with dc bias; therefore, choose a capacitor that is 1.5 times the
calculated value.
Compensation Selection
Calculate the compensation component values for the feedback
loop using the following equations:
SW
to Load Transient
C
C
C
C
R
OUT
OUT
OUT
COMP
COMP
= 1.5 × 22 µF = 32 µF
(
(
MIN
MIN
=
=
)
0
)
2
9 .
≅
≅
×
0
×
π
8
5 .
×
2
×
×
700
×
f
ZERO
700
π
Test Conditions/Comments
Fixed at 0.3 A for the
1% of V
2% of V
g
1
×
m
kHz
f
kHz
×
×
CROSSOVER
G
R
×
3
CS
COMP
OUT
OUT
(
×
50
0
0
1 .
3 .
mV
V
×
A
C
≈
−
OUT
22
0
3 .
V
µ
ADP2442
×
REF
A
F
V
×
OUT
5
mΩ
)
=
Value
0.3 A
50 mV
100 mV
5 mΩ
700 kHz
1
1 .
μF
Rev. 0 | Page 25 of 36
Selecting the crossover frequency to be 1/12 of the switching
frequency and placing the zero frequency at 1/8 of the crossover
frequency ensures that there is adequate phase margin in the
system.
Table 13. Calculated Parameter Value
Parameter
f
f
V
g
G
C
V
Based on the values listed in Table 13, calculate the compen-
sation value:
The closest standard resistor value is 118 kΩ. Therefore,
SYSTEM CONFIGURATION
Configure the system as follows; though the steps are not
sequential, they all must be completed:
•
•
•
•
•
See Figure 63 for a schematic of this design example and Table 14
for the calculated component values.
CROSSOVER
ZERO
REF
m
OUT
OUT
CS
Connect a capacitor of 1 µF between the VCC and PGND
pins and another capacitor of 1 µF between the VCC and
AGND pins. For best performance, use ceramic X5R or
X7R capacitors with a 25 V voltage rating.
Connect a ceramic capacitor of 10 nF with a 50 V voltage
rating between the BST and SW pins.
Connect a resistor between the FREQ and AGND pins as
close as possible to the IC.
If using the power-good feature, connect a 50 kΩ pull-up
resistor to a 5 V external supply.
For synchronization, connect an external clock with a
frequency of 700 kHz to the SYNC/MODE pin. Connect
the external clock to AGND to activate pulse skip mode or
connect it to VCC for forced fixed frequency mode.
C
R
COMP
COMP
=
=
0
2
9 .
×
×
π
Test Conditions/Comments
1/12 of f
1/8 of f
Fixed reference
Transconductance of error
amplifier
Current sense gain
Output capacitor
Output voltage
2
×
×
7
250
1
π
3 .
×
×
×
CROSSOVER
118
58
SW
2
3 .
=
×
185
22
0
6 .
×
pF
5
≈
≈
180
121
pF
kΩ
ADP2442
Value
58.3 kHz
7.3 kHz
0.6 V
250 µA/V
2 A/V
22 µF
5 V