MT41J64M16LA-187E:B TR Micron Technology Inc, MT41J64M16LA-187E:B TR Datasheet - Page 176
![IC DDR3 SDRAM 1GBIT 96FBGA](/photos/7/23/72317/mfg557-60-fbga_sml.jpg)
MT41J64M16LA-187E:B TR
Manufacturer Part Number
MT41J64M16LA-187E:B TR
Description
IC DDR3 SDRAM 1GBIT 96FBGA
Manufacturer
Micron Technology Inc
Type
DDR3 SDRAMr
Specifications of MT41J64M16LA-187E:B TR
Format - Memory
RAM
Memory Type
DDR3 SDRAM
Memory Size
1G (64M x 16)
Speed
533MHz
Interface
Parallel
Voltage - Supply
1.425 V ~ 1.575 V
Operating Temperature
0°C ~ 95°C
Package / Case
96-FBGA
Organization
64Mx16
Density
1Gb
Address Bus
16b
Maximum Clock Rate
1.066GHz
Operating Supply Voltage (typ)
1.5V
Package Type
FBGA
Operating Temp Range
0C to 95C
Operating Supply Voltage (max)
1.575V
Operating Supply Voltage (min)
1.425V
Supply Current
265mA
Pin Count
96
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
557-1378-2
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Asynchronous to Synchronous ODT Mode Transition (Power-Down Exit)
PDF: 09005aef826aa906/Source: 09005aef82a357c3
1Gb_DDR3_5.fm - Rev. F 11/08 EN
The DRAM’s ODT may exhibit either asynchronous or synchronous behavior during
power-down exit (PDX). This transition period occurs if the DLL is selected to be off
when in precharge power-down mode by setting MR0[12] to “0.” Power-down exit begins
t
registered HIGH.
The transition period is
ODT assertion during power-down exit results in an R
t
t
down exit may result in an R
ODTL off ×
ODTL off ×
If the AL has a large value, the uncertainty of the R
because ODTL on and ODTL off are derived from the WL, and WL is equal to CWL + AL.
Figure 121 on page 177 shows three different cases:
• ODT C: asynchronous behavior before
• ODT B: ODT state changes during the transition period, with
• ODT A: ODT state changes after the transition period with synchronous response
ANPD prior to CKE first being registered HIGH, and it ends
AONPD (MIN) and ODTL on ×
AONPD (MAX) and ODTL on ×
ODTL off ×
t
AOFPD (MAX)
t
t
CK +
CK +
t
CK +
t
t
t
AOF (MIN) or as late as the greater of
AOF (MAX). Table 83 on page 175 summarizes these parameters.
ANPD is equal to the greater of ODTL off + 1
t
AOF (MIN) and ODTL off ×
t
ANPD plus
TT
176
change as early as the lesser of
t
t
CK +
CK +
t
XPDLL.
t
t
AON (MIN) or as late as the greater of
AON (MAX). ODT de-assertion during power-
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
ANPD
1Gb: x4, x8, x16 DDR3 SDRAM
t
CK +
TT
state becomes quite large. This is
TT
t
On-Die Termination (ODT)
AOF (MAX) greater than
t
AOFPD (MAX) and
change as early as the lesser of
t
XPDLL after CKE is first
t
t
©2006 Micron Technology, Inc. All rights reserved.
AOFPD (MIN) and
CK or ODTL on + 1
t
AOFPD (MIN) less than
t
CK.
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