MT41J64M16LA-187E:B Micron Technology Inc, MT41J64M16LA-187E:B Datasheet
MT41J64M16LA-187E:B
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MT41J64M16LA-187E:B Summary of contents
Page 1
... Backward compatible to 1066 (-187E). Notes: 2. Backward compatible to 1333 (-15E). PDF: 09005aef826aa906 1Gb_DDR3_SDRAM.pdf – Rev. J 05/10 EN Products and specifications discussed herein are subject to change by Micron without notice. 1Gb: x4, x8, x16 DDR3 SDRAM 1 Options • Configuration – 256 Meg x 4 – 128 Meg x 8 – ...
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... -15E G JT -187 -187E for available offerings. 2 Micron Technology, Inc. reserves the right to change products or specifications without notice. 1Gb: x4, x8, x16 DDR3 SDRAM 128 Meg Meg Meg banks 8K 16K (A[13:0]) 8K (A[12:0]) 8 (BA[2:0]) 8 (BA[2:0]) 1K (A[9:0]) 1K (A[9:0]) : Revision :B/:D/:F/:G Revision ...
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... READ ........................................................................................................................................................ 113 WRITE ...................................................................................................................................................... 114 PRECHARGE ............................................................................................................................................. 114 REFRESH .................................................................................................................................................. 115 SELF REFRESH .......................................................................................................................................... 116 PDF: 09005aef826aa906 1Gb_DDR3_SDRAM.pdf – Rev. J 05/10 EN 1Gb: x4, x8, x16 DDR3 SDRAM 3 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2006 Micron Technology, Inc. All rights reserved. ...
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... Synchronous ODT Mode ............................................................................................................................... 194 ODT Latency and Posted ODT ................................................................................................................... 194 Timing Parameters .................................................................................................................................... 194 PDF: 09005aef826aa906 1Gb_DDR3_SDRAM.pdf – Rev. J 05/10 EN 1Gb: x4, x8, x16 DDR3 SDRAM 4 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2006 Micron Technology, Inc. All rights reserved. ...
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... Asynchronous to Synchronous ODT Mode Transition (Power-Down Exit) ....................................................... 203 Asynchronous to Synchronous ODT Mode Transition (Short CKE Pulse) ..................................................... 205 PDF: 09005aef826aa906 1Gb_DDR3_SDRAM.pdf – Rev. J 05/10 EN 1Gb: x4, x8, x16 DDR3 SDRAM 5 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2006 Micron Technology, Inc. All rights reserved. ...
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... DVAC) for CK - CK# and DQS - DQS# .............................................. 51 Characteristics 1.5V ................................................................ 63 DD DDQ Characteristics 1.575V ............................................................ 63 DD DDQ Characteristics 1.425V ............................................................ 64 DD DDQ 6 1Gb: x4, x8, x16 DDR3 SDRAM .................................................................... 41 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2006 Micron Technology, Inc. All rights reserved. ...
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... DH – AC150/DC100-Based ....................................................................... 104 t DH – AC135/DC100-Based ....................................................................... 105 (Below V ) for Valid Transition ............................................. 105 IH(AC) IL(AC) ............................................................................................................. 190 ............................................................................................................. 190 7 1Gb: x4, x8, x16 DDR3 SDRAM Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2006 Micron Technology, Inc. All rights reserved. ...
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... IH (Command and Address – Clock) .......................................................... 100 t t VAC for DS (DQ – Strobe) ........................................................................ 106 t DH (DQ – Strobe) ...................................................................................... 107 8 1Gb: x4, x8, x16 DDR3 SDRAM Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2006 Micron Technology, Inc. All rights reserved. ...
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... Rev. J 05/ MRD) ......................................................................................... 130 t MOD) .................................................................................. 131 t RCD (MIN) ............................................................................. 151 t DQSQ and Data Valid Window ................................................................... 160 and HZ .............................................................................................. 162 9 1Gb: x4, x8, x16 DDR3 SDRAM Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2006 Micron Technology, Inc. All rights reserved. ...
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... Figure 122: Transition Period for Short CKE HIGH Cycles with Entry and Exit Period Overlapping ................... 207 PDF: 09005aef826aa906 1Gb_DDR3_SDRAM.pdf – Rev. J 05/10 EN 1Gb: x4, x8, x16 DDR3 SDRAM 10 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2006 Micron Technology, Inc. All rights reserved. ...
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... PRE, PREA Writing PRE, PREA Precharging PREA = PRECHARGE ALL READ = RD, RDS4, RDS8 READ AP = RDAP, RDAPS4, RDAPS8 REF = REFRESH RESET = START RESET PROCEDURE SRE = Self refresh entry 11 1Gb: x4, x8, x16 DDR3 SDRAM State Diagram SRE SRX REF Refreshing PDE PDX Precharge power- down ...
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... DQS after the WRITE preamble, and output data is referenced on the first rising edge of DQS after the READ preamble. Read and write accesses to the DDR3 SDRAM are burst-oriented. Accesses start at a se- lected location and continue for a programmed number of locations in a programmed sequence ...
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... Connect UDQS to ground via 1K* resistor. – Connect UDQS – Connect UDM to V – Connect DQ 8–15 individually to either V DQ 8–15. *If ODT is used, 1K resistor should be changed to 4X that of the selected ODT. PDF: 09005aef826aa906 1Gb_DDR3_SDRAM.pdf – Rev. J 05/10 EN 1Gb: x4, x8, x16 DDR3 SDRAM via 1K* resistor. DD via 1K* resistor ...
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... Functional Block Diagrams DDR3 SDRAM is a high-speed, CMOS dynamic random access memory internally configured as an 8-bank DRAM. Figure 3: 256 Meg x 4 Functional Block Diagram ODT ZQ RZQ RESET# ZQCL, ZQCS CKE Control V SSQ logic A12 CK, CK# BC4 (burst chop) CS# RAS# OTF CAS# ...
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... I/O gating DM mask logic Bank control logic (128 x128) Column decoder Column- 7 address counter/ 3 latch Columns 0, 1, and 2 15 1Gb: x4, x8, x16 DDR3 SDRAM Functional Block Diagrams ODT control V R Columns 0, 1, and 2 TT,nom CK, CK# sw1 DLL READ FIFO 64 8 DQ[7:0] and ...
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... DD V RESET# A13 SS x4 and x8 are the same. Example D7 = NF, NF/TDQS#. NF applies to the x4 configuration only. NF/TDQS# applies to the x8 configuration only—selectable between NF or TDQS# via MRS (symbols are de- fined in Table 3). 16 1Gb: x4, x8, x16 DDR3 SDRAM Ball Assignments and Descriptions NF, NF/TDQS# SS ...
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... RESET# A13 and x8 are the same. Example D7 = NF, NF/TDQS#. NF applies to the x4 configuration only. NF/TDQS# applies to the x8 configuration only—selectable between NF or TDQS# via MRS (symbols are de- fined in Table 4). 17 1Gb: x4, x8, x16 DDR3 SDRAM Ball Assignments and Descriptions NF, NF/TDQS DM, DM/TDQS SSQ ...
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... DD V RESET and x8 are the same. Example D7 = NF, NF/TDQS#. NF applies to the x4 configuration only. NF/TDQS# applies to the x8 configuration only—selectable between NF or TDQS# via MRS (symbols are de- fined in Table 5). 18 1Gb: x4, x8, x16 DDR3 SDRAM Ball Assignments and Descriptions DQ12 V V DDQ ...
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... Output data strobe (DQS, DQS#) is referenced to the crossings of CK and CK#. Clock enable: CKE enables (registered HIGH) and disables (registered LOW) internal circuitry and clocks on the DRAM. The specific circuitry that is enabled/disabled is dependent upon the DDR3 SDRAM configuration and operating mode. Taking CKE LOW provides PRECHARGE POWER-DOWN and SELF REFRESH operations (all banks idle), or active power-down (row active in any bank) ...
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... No connect: These balls should be left unconnected (the ball has no connection to the DRAM or to other balls). No function: When configured device, these balls are NF. When configured device, these balls are defined as TDQS#, DQ[7:4]. 20 1Gb: x4, x8, x16 DDR3 SDRAM Ball Assignments and Descriptions REFCA must be maintained at all times (excluding self . ...
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... Output data strobe (DQS, DQS#) is referenced to the crossings of CK and CK#. Clock enable: CKE enables (registered HIGH) and disables (registered LOW) internal circuitry and clocks on the DRAM. The specific circuitry that is enabled/disabled is dependent upon the DDR3 SDRAM configuration and operating mode. Taking CKE LOW provides PRECHARGE POWER-DOWN and SELF REFRESH operations (all banks idle), or active power-down (row active in any bank) ...
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... No connect: These balls should be left unconnected (the ball has no connection to the DRAM or to other balls). No function: When configured device, these balls are NF. When configured device, these balls are defined as TDQS#, DQ[7:4]. 22 1Gb: x4, x8, x16 DDR3 SDRAM Ball Assignments and Descriptions REFCA must be maintained at all times (excluding self . ...
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... Output data strobe (DQS, DQS#) is referenced to the crossings of CK and CK#. Clock enable: CKE enables (registered HIGH) and disables (registered LOW) internal circuitry and clocks on the DRAM. The specific circuitry that is enabled/disabled is dependent upon the DDR3 SDRAM configuration and operating mode. Taking CKE LOW provides PRECHARGE POWER-DOWN and SELF REFRESH operations (all banks idle),or active power-down (row active in any bank) ...
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... External reference ball for output drive calibration: This ball is tied to an external 240Ω resistor (RZQ), which is tied connect: These balls should be left unconnected (the ball has no connection to the DRAM or to other balls). 24 1Gb: x4, x8, x16 DDR3 SDRAM Ball Assignments and Descriptions . REFCA must be maintained at all times (excluding self ...
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... Rev. J 05/10 EN 0.8 ±0.1 8 ±0.1 Ball 11.5 ±0 6.4 CTR 25 1Gb: x4, x8, x16 DDR3 SDRAM Package Dimensions Ball A1 ID 1.2 MAX 0.25 MIN Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2006 Micron Technology, Inc. All rights reserved. ...
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... Rev. J 05/10 EN 0.8 ±0.1 Ball 11.5 ±0. Micron Technology, Inc. reserves the right to change products or specifications without notice. 1Gb: x4, x8, x16 DDR3 SDRAM Package Dimensions Ball A1 ID 1.2 MAX 0.25 MIN © 2006 Micron Technology, Inc. All rights reserved. ...
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... Rev. J 05/10 EN 0.8 ±0.1 Ball 15.5 ±0. Micron Technology, Inc. reserves the right to change products or specifications without notice. 1Gb: x4, x8, x16 DDR3 SDRAM Package Dimensions Ball A1 ID 1.2 MAX 0.25 MIN © 2006 Micron Technology, Inc. All rights reserved. ...
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... Rev. J 05/10 EN 0.8 ±0.1 Ball 15.5 ±0. Micron Technology, Inc. reserves the right to change products or specifications without notice. 1Gb: x4, x8, x16 DDR3 SDRAM Package Dimensions Ball A1 ID 1.2 MAX 0.25 MIN © 2006 Micron Technology, Inc. All rights reserved. ...
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... Ball ±0. 0.8 TYP 6.4 CTR 8 ±0.15 29 1Gb: x4, x8, x16 DDR3 SDRAM Package Dimensions Ball A1 ID 1.2 MAX 0.25 MIN Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2006 Micron Technology, Inc. All rights reserved. ...
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... Voltage on any pin relative OUT T Operating case temperature C T Storage temperature STG 1. V Notes: 2. MAX operating case temperature Device functionality is not guaranteed if the DRAM device exceeds the maximum T PDF: 09005aef826aa906 1Gb_DDR3_SDRAM.pdf – Rev. J 05/10 EN Min –0.4 SS –0.4 SSQ –0 –55 and V ...
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... DDQ OUT = C (DQ) - 0.5 × (C [DQS DIO IO IO 0], BA[2:0 (CTRL) - 0.5 × (C [CK DI_CTRL (CMD_ADDR) - 0.5 × (C DI_CMD_ADDR I 31 1Gb: x4, x8, x16 DDR3 SDRAM Electrical Specifications 0.8 1.4 0.8 1.4 0.8 0 0.15 0 0.15 0 0.15 1.5 2.5 1.5 2.3 1.4 1.5 2.5 1 ...
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... Junction-to-case (TOP) Notes: 1. MAX operating case temperature thermal solution must be designed to ensure the DRAM device does not exceed the 3. Device functionality is not guaranteed if the DRAM device exceeds the maximum The thermal resistance data is based off of a number of samples from multiple lots and ...
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... I x16 RFC 1Gb 44 44 2Gb 64 64 4Gb 120 120 PDF: 09005aef826aa906 1Gb_DDR3_SDRAM.pdf – Rev. J 05/10 EN Electrical Specifications – I Specifications and Conditions Definitions DD measurement tables, the following definitions and conditions DD ≤ V ≥ HIGH IL(AC)max REF DD set to RZQ/7 (34Ω) set to RZQ/6 (40Ω) set to RZQ/2 (120Ω ...
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... DQ, DQS, DQS# are midlevel. Notes LOW. 3. Only selected bank (single) active. PDF: 09005aef826aa906 1Gb_DDR3_SDRAM.pdf – Rev. J 05/10 EN Electrical Specifications – I ACT ...
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... DQ, DQS, DQS# are midlevel unless driven as required by the RD command. Notes LOW. 3. Burst sequence is driven on each DQ signal by the RD command. 4. Only selected bank (single) active. PDF: 09005aef826aa906 1Gb_DDR3_SDRAM.pdf – Rev. J 05/10 EN Electrical Specifications – I ACT ...
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... Idle banks Special notes 1. MR0[12] defines DLL on/off behavior during precharge power-down only; DLL on (fast Notes: 2. “Enabled, off“ means the MR bits are enabled, but the signal is LOW. PDF: 09005aef826aa906 1Gb_DDR3_SDRAM.pdf – Rev. J 05/10 EN Electrical Specifications – I Precharge I Precharge DD2P1 Power-Down ...
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... Notes: 1. DQ, DQS, DQS# are midlevel LOW. 3. All banks closed. PDF: 09005aef826aa906 1Gb_DDR3_SDRAM.pdf – Rev. J 05/10 EN Electrical Specifications – Repeat sub-loop 0, use BA[2: Repeat sub-loop 0, use BA[2: Repeat sub-loop 0, use BA[2: ...
Page 38
... DQ, DQS, DQS# are midlevel when not driving in burst sequence. Notes LOW. 3. Burst sequence is driven on each DQ signal by the RD command. 4. All banks open. PDF: 09005aef826aa906 1Gb_DDR3_SDRAM.pdf – Rev. J 05/10 EN Electrical Specifications – ...
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... DQ, DQS, DQS# are midlevel when not driving in burst sequence. Notes LOW. 3. Burst sequence is driven on each DQ signal by the WR command. 4. All banks open. PDF: 09005aef826aa906 1Gb_DDR3_SDRAM.pdf – Rev. J 05/10 EN Electrical Specifications – ...
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... DD5B 5–8 1c 9–12 1d 13–16 1e 17–20 1f 21–24 1g 25–28 1h 29–32 2 33–nRFC - 1 1. DQ, DQS, DQS# are midlevel. Notes LOW. PDF: 09005aef826aa906 1Gb_DDR3_SDRAM.pdf – Rev. J 05/10 EN Electrical Specifications – I REF Repeat sub-loop 1a, use BA[2: Repeat sub-loop 1a, use BA[2: ...
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... Idle banks SRT ASR 1. "Enabled, midlevel" means the MR command is enabled, but the signal is midlevel. Notes: 2. During a cold boot RESET (initialization), current reading is valid once power is stable PDF: 09005aef826aa906 1Gb_DDR3_SDRAM.pdf – Rev. J 05/10 EN Electrical Specifications – and I DD6 DD6ET : Self Refresh Current ...
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... PDF: 09005aef826aa906 1Gb_DDR3_SDRAM.pdf – Rev. J 05/10 EN Electrical Specifications – I ACT RDA ...
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... DQ, DQS, DQS# are midlevel unless driven as required by the RD command. Notes LOW. 3. Burst sequence is driven on each DQ signal by the RD command CL-1. PDF: 09005aef826aa906 1Gb_DDR3_SDRAM.pdf – Rev. J 05/10 EN Electrical Specifications – I Repeat sub-loop 11, use BA[2: Repeat sub-loop 10, use BA[2: Repeat sub-loop 11, use BA[2: ...
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... DD (MAX) = +85° +85°C; ASR and ODT are disabled; SRT is enabled. C values must be derated (increased) on IT-option and AT-option devices when op- DD erated outside of the range 0°C ≤ 1Gb: x4, x8, x16 DDR3 SDRAM Specifications DD DDR3-1600 Units 85 95 110 120 110 120 ...
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... I and I must be derated by 7%. DD6 DD7 6b. When T > +85° DD0 DD1 DD2N must be derated by 2%; I must be derated by 30%; and I DD2Px 45 1Gb: x4, x8, x16 DDR3 SDRAM DD must be derated by 4%; I and I DD4R , DD2NT DD2Q DD3N DD3P DD4R must be derated by 80%. DD6 Micron Technology, Inc. reserves the right to change products or specifications without notice. © ...
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... Input reference voltage command/address bus I/O reference voltage DQ bus I/O reference voltage DQ bus in SELF REFRESH Command/address termination voltage (system level, not direct DRAM input Notes values are determined to be less than 20 MHz in frequency. DRAM must meet specifi PDF: 09005aef826aa906 1Gb_DDR3_SDRAM.pdf – Rev. J 05/10 EN Symbol V DD ...
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... IL(DC100)max – V IL(AC135)max V –150 IL(AC150)max V –175 IL(AC175)max REF slew rates and setup/hold times are specified at the DRAM ball. V and DM inputs and t IH and 900mV (peak-to-peak). 47 1Gb: x4, x8, x16 DDR3 SDRAM Electrical Specifications – DC and AC and back to V when in SELF REFRESH, with- ...
Page 48
... V IL(DC) 0.575V V IL(AC) Note: 1. Numbers in diagrams reflect nominal values. PDF: 09005aef826aa906 1Gb_DDR3_SDRAM.pdf – Rev. J 05/10 EN 1Gb: x4, x8, x16 DDR3 SDRAM Electrical Specifications – DC and AC V and V levels with ringback IL IH 1.90V 1.50V 0.925V 0.850V 0.780V 0.765V 0.750V ...
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... Vns DD DDQ /V (see Figure 17) 0.25 Vns SS SSQ Maximum amplitude /V DDQ SSQ Maximum amplitude 49 1Gb: x4, x8, x16 DDR3 SDRAM Electrical Specifications – DC and AC DDR3-1066 DDR3-1333 0.4V 0.4V 0.4V 0.4V 0.4V 0.4V 0.5 Vns 0.4 Vns 0.5 Vns 0.4 Vns DDR3-1066 DDR3-1333 0.4V ...
Page 50
... V the differential slew rate of CK, CK# is greater than 3 V/ns. must provide 25mV (single-ended) of the voltages separation. IX DDQ DDQ , V SSQ 50 1Gb: x4, x8, x16 DDR3 SDRAM Electrical Specifications – DC and AC Min Max +200 n/a n/a –200 - IH(AC) REF ...
Page 51
... SEL,max SSQ t DVAC t DVAC 0.0 half cycle Slew Rate (V/ns) >4.0 4.0 3.0 2.0 1.9 1.6 51 1Gb: x4, x8, x16 DDR3 SDRAM Electrical Specifications – DC and DQS V SEL CK - CK# DQS - DQS# t DVAC t DVAC) for CK - CK# and DQS - t DVAC (ps IH,diff(AC) IL,diff(AC) 350mV 75 57 ...
Page 52
... V IL(DC)max and the first crossing of V Measured Edge From Rising V REF Falling V REF Rising V IL(DC)max Falling V IH(DC)min 52 1Gb: x4, x8, x16 DDR3 SDRAM Electrical Specifications – DC and AC t DVAC) for CK - CK# and DQS - t DVAC (ps IH,diff(AC) IL,diff(AC) 350mV Setup ( IH(AC)min . . Hold ( REF (see Figure 21 (page 53)) ...
Page 53
... Figure 21: Nominal Slew Rate Definition for Single-Ended Input Signals Setup Hold PDF: 09005aef826aa906 1Gb_DDR3_SDRAM.pdf – Rev. J 05/10 EN Electrical Specifications – DC and AC ΔTFS ΔTFH 53 Micron Technology, Inc. reserves the right to change products or specifications without notice. 1Gb: x4, x8, x16 DDR3 SDRAM ΔTRS V IH(AC)min V IH(DC)min V or REFDQ V ...
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... PDF: 09005aef826aa906 1Gb_DDR3_SDRAM.pdf – Rev. J 05/10 EN IL,diff,max Slew Rates Measured Edge From Rising V IL,diff,max Falling V IH,diff,min ΔTF diff 54 1Gb: x4, x8, x16 DDR3 SDRAM Electrical Specifications – DC and AC and V . The nominal slew rate for a IH,diff,min and V IH,diff,min IL,diff,max To Calculation V V IH,diff,min IH,diff,min ΔTR,diff V ...
Page 55
... Vddq vice operates between –40°C and 0° targeted to provide: TT 120Ω is made TT120(PD240) 60Ω is made and R TT60(PD120) 55 1Gb: x4, x8, x16 DDR3 SDRAM ODT Characteristics and R ) are defined as follows: TT(PU) TT(PD) is turned off TT(PD) is turned off TT(PU) Nom ...
Page 56
... V DDQ 0.5 × V DDQ 0.8 × V DDQ 0.2 × V DDQ 0.5 × V DDQ 0.8 × V DDQ IL(AC) IH(AC) 56 1Gb: x4, x8, x16 DDR3 SDRAM ODT Characteristics TT40(PU80) TT30(PU60) TT20(PU40) Min Nom Max 0.6 1.0 1.1 0.9 1.0 1.1 0.9 1.0 1.4 ...
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... DDQ Change Min DDQ 57 Micron Technology, Inc. reserves the right to change products or specifications without notice. 1Gb: x4, x8, x16 DDR3 SDRAM ODT Characteristics Nom Max 1.0 1.1 1.0 1.1 1.0 1.4 1.0 1.4 1.0 1.1 1.0 1.1 1.0 1.6 Max dV × |DV| ...
Page 58
... RZQ/4 (60Ω) n/a RZQ/12 (20Ω) n/a RZQ/4 (60Ω) n/a RZQ/12 (20Ω) n/a RZQ/12 (20Ω) RZQ/2 (120Ω) stable temperature and voltage (V 58 1Gb: x4, x8, x16 DDR3 SDRAM ODT Characteristics SSQ V SSQ Figure 25 (page 59) SSQ Figure 25 (page 59) RTT,nom Figure 26 (page 59) ...
Page 59
... SW2 T SW1 V V SW2 SW2 V SW1 End point: Extrapolated point at V SSQ 59 Micron Technology, Inc. reserves the right to change products or specifications without notice. 1Gb: x4, x8, x16 DDR3 SDRAM ODT Characteristics V /2 DDQ t AOF End point: Extrapolated point at V RTT,nom V RTT,nom T SW1 T ...
Page 60
... ODTL cnw t ADC T SW21 T V SW11 SW2 RTT,nom V SW1 V RTT(WR) 60 1Gb: x4, x8, x16 DDR3 SDRAM ODT Characteristics 4 or ODTL 8 cwn cwn t ADC V RTT,nom T SW22 T SW12 End point: Extrapolated point at V RTT(WR) Micron Technology, Inc. reserves the right to change products or specifications without notice. ...
Page 61
... Chip in drive mode Output driver ON(PU) I OUT R ON(PD Micron Technology, Inc. reserves the right to change products or specifications without notice. 1Gb: x4, x8, x16 DDR3 SDRAM Output Driver Impedance and R ) are defined as fol- ON(PU) ON(PD) is turned off ON(PD) is turned off V DDQ DQ V OUT ...
Page 62
... R at 0.5 × V ON(PU) ON(PD) Ron - Ron × 100 PUPD Ron NOM vice operates between –40°C and 0° 1Gb: x4, x8, x16 DDR3 SDRAM Output Driver Impedance ON34 Nom Max 1.0 1.1 1.0 1.1 1.0 1.4 1.0 1.4 1.0 1.1 1.0 1 ...
Page 63
... I @ 0.8 × DDQ I @ 0.2 × DDQ I @ 0.5 × DDQ I @ 0.8 × DDQ 63 1Gb: x4, x8, x16 DDR3 SDRAM Output Driver Impedance = 1.57V, and Table 40 (page 64) for DD ON34(PD) is turned off is turned off Min Nom Max 237.6 240 242.4 33.9 34.3 34.6 Min Nom Max 20 ...
Page 64
... Min dR dTM dVM dTL dVL dTH dVH 1Gb: x4, x8, x16 DDR3 SDRAM Output Driver Impedance = 1.425V Max Nom Min 14.0 8.3 7.5 23.3 20.8 18.7 37.3 33.3 23.5 37.3 33.3 23.5 23.3 20.8 18.7 14.0 8.3 7.5 Max dTL × |Δ dVL × ...
Page 65
... ON ON dTL × |Δ dVL × |Δ dTM × |Δ dVM × |ΔV| ON dTH × |Δ dVH × |Δ DDQ 65 1Gb: x4, x8, x16 DDR3 SDRAM Output Driver Impedance Min Nom Max 0.6 1.0 1.1 0.9 1.0 1.1 0.9 1.0 1.4 0.9 1 ...
Page 66
... ON dR dVL dTH dVH Micron Technology, Inc. reserves the right to change products or specifications without notice. 1Gb: x4, x8, x16 DDR3 SDRAM Output Driver Impedance Max Unit 1.5 %/°C 0.15 %/mV 1.5 %/°C 0.15 %/mV 1.5 %/°C 0.15 %/mV © 2006 Micron Technology, Inc. All rights reserved. ...
Page 67
... Output Characteristics and Operating Conditions The DRAM uses both single-ended and differential output drivers. The single-ended out- put driver is summarized below, while the differential output driver is summarized in Table 46 while the differential output driver is summarized in Table 47 (page 68). Table 46: Single-Ended Output Driver Characteristics ...
Page 68
... V OL,diff(AC) MM PUPD Output calibration has been performed at a stable temperature and voltage ( SSQ /2; slew rate @ 5 V/ns, interpolate for faster slew rate. REF DDQ 68 1Gb: x4, x8, x16 DDR3 SDRAM Min Max – 150 V + 150 REF REF +0.2 × V DDQ –0.2 × V DDQ – ...
Page 69
... DDQ V DUT REF 25Ω TT DQS DQS# Timing reference point ZQ RZQ = 240Ω 69 1Gb: x4, x8, x16 DDR3 SDRAM DDQ V SS Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2006 Micron Technology, Inc. All rights reserved. MAX output V OH ...
Page 70
... Figure 32: Nominal Slew Rate Definition for Single-Ended Output Signals PDF: 09005aef826aa906 1Gb_DDR3_SDRAM.pdf – Rev. J 05/10 EN Output Characteristics and Operating Conditions and V OL(AC) Edge From DQ Rising V OL(AC) Falling V OH(AC) Δ 1Gb: x4, x8, x16 DDR3 SDRAM for single-ended signals. OH(AC) Measured To Calculation V V OH(AC) OH(AC OL(AC) OH(AC) Δ OH(AC) ...
Page 71
... Output Characteristics and Operating Conditions and V OL(AC) OH(AC) Measured Edge From Rising V OL,diff(AC) Falling V OH,diff(AC) ΔTF diff 71 Micron Technology, Inc. reserves the right to change products or specifications without notice. 1Gb: x4, x8, x16 DDR3 SDRAM for differential signals. To Calculation OH,diff(AC) OH,diff(AC) OL,diff(AC) ΔTR diff OL,diff(AC) OH,diff(AC) OL,diff(AC) Δ ...
Page 72
... CK (AVG) 1.875 t CK (AVG) Reserved t CK (AVG) 1.875 REFI depends OPER both CL and CWL requirement settings need to be fulfilled. 72 1Gb: x4, x8, x16 DDR3 SDRAM Speed Bin Tables -187 8-8-8 Max Min Max Units – – 15 – – 15 – – 52.5 ...
Page 73
... Reserved t CK (AVG) Reserved t CK (AVG) 1 (AVG) Reserved t CK (AVG) 1 REFI depends OPER both CL and CWL requirement settings need to be fulfilled. 73 1Gb: x4, x8, x16 DDR3 SDRAM Speed Bin Tables 1 2 -15 10-10-10 Max Min Max – – 15 – – 15 – – REFI ...
Page 74
... CK (AVG (AVG (AVG (AVG (AVG (AVG (AVG (AVG) (-187E). t REFI depends OPER both CL and CWL requirement settings need to be fulfilled. 74 1Gb: x4, x8, x16 DDR3 SDRAM Speed Bin Tables 1 -125 11-11-11 Min Max Units – 13.75 ns – 13.75 ns – 48. REFI ns 3.0 3 ...
Page 75
... CK (AVG (AVG (AVG (AVG (AVG (AVG (AVG (AVG) (-187E). t REFI depends OPER both CL and CWL requirement settings need to be fulfilled. 75 1Gb: x4, x8, x16 DDR3 SDRAM Speed Bin Tables 1 -107 13-13-13 Min Max Units 13.91 20 – 13.91 ns – 13.91 ns – 48. REFI ns 3 ...
Page 76
Electrical Characteristics and AC Operating Conditions Table 54: Electrical Characteristics and AC Operating Conditions Notes 1–8 apply to the entire table Parameter Clock period average 0°C to 85°C C DLL disable mode T = >85°C to 95°C C ...
Page 77
Table 54: Electrical Characteristics and AC Operating Conditions (Continued) Notes 1–8 apply to the entire table Parameter Data setup time to Base (specification) DQS, DQS V/ns REF Data setup time to Base (specification) DQS, DQS ...
Page 78
Table 54: Electrical Characteristics and AC Operating Conditions (Continued) Notes 1–8 apply to the entire table Parameter DQS, DQS# High-Z time (RL + BL/2) DQS, DQS# differential READ preamble DQS, DQS# differential READ postamble DLL locking time CTRL, CMD, ADDR ...
Page 79
Table 54: Electrical Characteristics and AC Operating Conditions (Continued) Notes 1–8 apply to the entire table Parameter MULTIPURPOSE REGISTER READ burst end to mode register set for multipurpose register exit ZQCL command: Long POWER-UP and RE- calibration time SET operation ...
Page 80
Table 54: Electrical Characteristics and AC Operating Conditions (Continued) Notes 1–8 apply to the entire table Parameter Valid clocks before self refresh exit, power-down exit, or reset exit CKE MIN pulse width Command pass disable delay Power-down entry to power-down ...
Page 81
Table 54: Electrical Characteristics and AC Operating Conditions (Continued) Notes 1–8 apply to the entire table Parameter R synchronous turn-on delay TT R synchronous turn-off delay TT R turn-on from ODTL on reference TT R turn-off from ODTL off reference ...
Page 82
... DS (base) and DH (base) values are for a single-ended 1 V/ns DQ slew rate and 2 V/ns differential DQS, DQS# slew rate. tion edge to its respective data strobe signal (DQS, DQS#) crossing. 82 1Gb: x4, x8, x16 DDR3 SDRAM ≤ +95°C and +1.5V ±0.075V DDQ output buffer selection. ...
Page 83
... When the device is operated with input clock jitter, this parameter needs to be derated 22. Single-ended signal parameter. 23. The DRAM output timing is aligned to the nominal or average clock. Most output param- 24. The maximum preamble is bound by 25. These parameters are measured from a data strobe signal (DQS, DQS#) crossing to its 26 ...
Page 84
... PER (MAX) and JITdty (MAX). The parameters 10 required to be derated by subtracting both off time maximum is when the DRAM buffer is in High-Z. The ODT reference load is shown in Figure 24 (page 58). This output load is used for ODT timings (see Figure 31 (page 69)). V and the consecutive crossing of V REF(DC) have at least one NOP command between it and another AUTO REFRESH command ...
Page 85
Electrical Characteristics and AC Operating Conditions Table 55: Electrical Characteristics and AC Operating Conditions for Speed Extensions Notes 1–8 apply to the entire table Parameter Clock period average: DLL disable mode T = 0°C to 85° >85°C ...
Page 86
Table 55: Electrical Characteristics and AC Operating Conditions for Speed Extensions (Continued) Notes 1–8 apply to the entire table Parameter Cumulative error across 2 cycles 3 cycles 4 cycles 5 cycles 6 cycles 7 cycles 8 cycles 9 cycles 10 ...
Page 87
Table 55: Electrical Characteristics and AC Operating Conditions for Speed Extensions (Continued) Notes 1–8 apply to the entire table Parameter DQS, DQS# rising to CK, CK# rising DQS, DQS# differential input low pulse width DQS, DQS# differential input high pulse ...
Page 88
Table 55: Electrical Characteristics and AC Operating Conditions for Speed Extensions (Continued) Notes 1–8 apply to the entire table Parameter ACTIVATE-to-PRECHARGE command period ACTIVATE-to-ACTIVATE command period ACTIVATE-to-ACTIVATE minimum com- 1KB page size mand 2KB page size period Four ACTIVATE 1KB ...
Page 89
Table 55: Electrical Characteristics and AC Operating Conditions for Speed Extensions (Continued) Notes 1–8 apply to the entire table Parameter Begin power supply ramp to power supplies stable RESET# LOW to power supplies stable RESET# LOW to I/O and R ...
Page 90
Table 55: Electrical Characteristics and AC Operating Conditions for Speed Extensions (Continued) Notes 1–8 apply to the entire table Parameter Power-down entry period: ODT either synchronous or asynchronous Power-down exit period: ODT either synchronous or asynchronous ACTIVATE command to power-down ...
Page 91
Table 55: Electrical Characteristics and AC Operating Conditions for Speed Extensions (Continued) Notes 1–8 apply to the entire table Parameter Asynchronous R turn-off delay TT (power-down with DLL off) ODT HIGH time with WRITE command and BL8 ODT HIGH time ...
Page 92
... DS (base) and DH (base) values are for a single-ended 1 V/ns DQ slew rate and 2 V/ns differential DQS, DQS# slew rate. tion edge to its respective data strobe signal (DQS, DQS#) crossing. 92 1Gb: x4, x8, x16 DDR3 SDRAM ≤ +95°C and +1.5V ±0.075V DDQ output buffer selection. ...
Page 93
... When the device is operated with input clock jitter, this parameter needs to be derated 22. Single-ended signal parameter. 23. The DRAM output timing is aligned to the nominal or average clock. Most output param- 24. The maximum preamble is bound by 25. These parameters are measured from a data strobe signal (DQS, DQS#) crossing to its 26 ...
Page 94
... PER (MAX) and JITdty (MAX). The parameters 10 required to be derated by subtracting both off time maximum is when the DRAM buffer is in High-Z. The ODT reference load is shown in Figure 24 (page 58). This output load is used for ODT timings (see Figure 31 (page 69)). V and the consecutive crossing of V REF(DC) have at least one NOP command between it and another AUTO REFRESH command ...
Page 95
... DDR3 SDRAM IS (base) + Δ IH(AC) IL(AC the time of the rising clock transi- IL(AC Setup ( IS) nominal slew rate IH(AC)min -to-AC region,” use the nominal slew rate for de- -to-AC region,” ...
Page 96
... DDR3 SDRAM = V - 175mV IL(AC) REF(DC) 1.6 V/ns 1.4 V/ns 1.2 V/ns Δ Δ Δ Δ Δ 104 66 112 ...
Page 97
... DDR3 SDRAM = V - 135mV IL(AC) REF(DC) 1.6 V/ns 1.4 V/ns 1.2 V/ns Δ Δ Δ Δ Δ ...
Page 98
... VAC at 150mV (ps) 175 170 167 163 162 161 159 155 0 150 0 150 98 1Gb: x4, x8, x16 DDR3 SDRAM t t VAC at 135mV (ps) VAC at 125mV (ps) 175 160 150 140 130 120 110 105 n/a n/a Micron Technology, Inc. reserves the right to change products or specifications without notice. ...
Page 99
... IS (Command and Address – Clock REF region Nominal slew rate t VAC Δ Setup slew rate REF(DC) IL(AC)max = ΔTF 99 1Gb: x4, x8, x16 DDR3 SDRAM VAC Nominal slew rate REF region Δ IH(AC)min REF(DC) = rising signal ΔTR Micron Technology, Inc. reserves the right to change products or specifications without notice. ...
Page 100
... Command and Address Setup, Hold, and Derating t IH (Command and Address – Clock REF region Nominal slew rate Δ REF(DC) IL(DC)max = ΔTR 100 1Gb: x4, x8, x16 DDR3 SDRAM Nominal slew rate REF region Δ IH(DC)min REF(DC) Hold slew rate = falling signal ΔTF Micron Technology, Inc. reserves the right to change products or specifications without notice. © ...
Page 101
... Command and Address Setup, Hold, and Derating t IS (Command and Address – Clock Nominal line to AC Tangent line t VAC Setup slew rate rising signal ΔTF Setup slew rate falling signal 101 1Gb: x4, x8, x16 DDR3 SDRAM VAC Tangent line REF region ΔTR Tangent line ( IH(DC)min REF(DC) = ΔTR ...
Page 102
... IH (Command and Address – Clock REF Tangen t line REF ΔTR Tangent line (V Hold slew rate = rising signal Tangent line (V Hold slew rate falling signal = 102 1Gb: x4, x8, x16 DDR3 SDRAM Nominal line Tangen t line Nominal line Δ REF(DC) IL(DC)max Δ ...
Page 103
... If the actual signal is always later than the nominal REF(DC) DDR3-1600 – – – – – 100 65 45 103 1Gb: x4, x8, x16 DDR3 SDRAM Data Setup, Hold, and Derating DS (base) + Δ DS. For a valid transition, /V for some time IH(AC) IL(AC the time of the rising clock transi- IL(AC Setup ( DS) nominal slew IH(AC)min -to-AC region,” ...
Page 104
... DQS, DQS# Differential Slew Rate 2.0 V/ns 1.8 V/ Δ Δ Δ Δ Δ –4 0 – –10 8 –2 8 –8 104 1Gb: x4, x8, x16 DDR3 SDRAM Data Setup, Hold, and Derating 1.6 V/ns 1.4 V/ns 1.2 V/ Δ Δ Δ Δ Δ –1 –10 7 –2 15 –11 –16 – ...
Page 105
... V IH(AC) IL(AC) t VAC at 175mV (ps) VAC at 150mV (ps) Min 105 1Gb: x4, x8, x16 DDR3 SDRAM Data Setup, Hold, and Derating 1.6 V/ns 1.4 V/ns 1.2 V/ Δ Δ Δ Δ Δ for Valid Transition t VAC at 135mV (ps) Min Min 175 187 ...
Page 106
... VAC for DS (DQ – Strobe Nominal slew rate t VAC Δ Setup slew rate REF(DC) IL(AC)max = rising signal ΔTF 106 1Gb: x4, x8, x16 DDR3 SDRAM Data Setup, Hold, and Derating VAC Nominal slew rate REF region Δ IH(AC)min REF(DC) = ΔTR Micron Technology, Inc. reserves the right to change products or specifications without notice. ...
Page 107
... Nominal slew rate Δ REF(DC) IL(DC)max Hold slew rate = falling signal ΔTR 107 Micron Technology, Inc. reserves the right to change products or specifications without notice. 1Gb: x4, x8, x16 DDR3 SDRAM Data Setup, Hold, and Derating Nominal slew rate REF region Δ IL(DC)min ...
Page 108
... Rev. J 05/ (DQ – Strobe Nominal to AC Tangent line t VAC Setup slew rate rising signal ΔTF Setup slew rate falling signal 108 1Gb: x4, x8, x16 DDR3 SDRAM Data Setup, Hold, and Derating VAC line Tangent line REF region ΔTR Tangent line ( IH(AC)min ...
Page 109
... DH REF Tangent line REF ΔTR Tangent line (V Hold slew rate = rising signal Tangent line (V Hold slew rate = falling signal 109 1Gb: x4, x8, x16 DDR3 SDRAM Data Setup, Hold, and Derating Nominal line Tangent line Nominal line Δ REF(DC) IL(DC)max ΔTR ...
Page 110
... Cycle CS# RAS# CAS# WE the clock. The MSB of BA, RA, and CA are device-, density-, and configuration-dependent. 110 1Gb: x4, x8, x16 DDR3 SDRAM Commands – Truth Tables BA [2:0] An A12 A10 code Row address (RA RFU RFU RFU RFU RFU RFU RFU RFU RFU RFU RFU ...
Page 111
... Self refresh exit is asynchronous. 8. Burst READs or WRITEs cannot be terminated or interrupted. MRS (fixed) and OTF BL/BC 9. The purpose of the NOP command is to prevent the DRAM from registering any unwan- 10. The DES and NOP commands perform similarly. 11. The power-down mode does not perform any REFRESH operations. ...
Page 112
... All states and sequences not shown are illegal or reserved unless explicitly described else Current state = The state of the DRAM immediately prior to clock edge n. 4. CKE (n) is the logic state of CKE at clock edge n; CKE ( was the state of CKE at the 5. COMMAND is the command registered at the clock edge (must be a legal command as 6 ...
Page 113
... Figure 50 (page 129)). This command may be issued at any time by the controller depending on the system environment. The ZQCL command triggers the calibration engine inside the DRAM. Af- ter calibration is achieved, the calibrated values are transferred from the calibration ...
Page 114
... Rev. J 05/10 EN CKE Prev. Next Cycle Cycle CS# RAS# CAS# WE RDS4 RDS8 RDAP CKE Prev. Next Cycle Cycle CS# RAS# CAS# WE 114 1Gb: x4, x8, x16 DDR3 SDRAM BA [3:0] An A12 RFU RFU RFU RFU RFU RFU H BA [3:0] An A12 RFU RFU RFU H L ...
Page 115
... However, the precharge period is determined by the last PRECHARGE command issued to the bank. REFRESH REFRESH is used during normal operation of the DRAM and is analogous to CAS#-before- RAS# (CBR) refresh or auto refresh. This command is nonpersistent must be issued each time a refresh is required. The addressing is generated by the internal re- fresh controller. This makes the address bits a “ ...
Page 116
... Only NOP and DES commands are allowed after a REFRESH command and until SELF REFRESH SELF REFRESH command is used to retain data in the DRAM, even if the rest of the system is powered down. When in self refresh mode, the DRAM retains data without external clocking. Self refresh mode is also a convenient method used to enable/disable the DLL as well as to change the clock frequency within the allowed synchronous oper- ating range (see Input Clock Frequency Change (page 121)) ...
Page 117
... DRAM is targeted, but not guaranteed, to operate similarly to the normal mode with a few notable exceptions: • The DRAM supports only one value of CAS latency ( and one value of CAS WRITE latency (CWL = 6). • DLL disable mode affects the read data clock-to-data strobe relationship ( ...
Page 118
... Starting from the idle state (all banks are precharged, all timings are fulfilled, ODT 2. After 3. Self refresh may be exited when the clock is stable with the new frequency for 4. After another 5. The DRAM will be ready for its next command in the DLL enable mode after the PDF: 09005aef826aa906 1Gb_DDR3_SDRAM.pdf – Rev. J 05/10 EN Ta0 ...
Page 119
... XS, then set MR1[ enable DLL. t MRD, then set MR0[ begin DLL RESET. t MRD, update registers (CL, CWL, and write recovery may be necessary). t MOD, any valid command. t CKSRX. TT,nom 119 1Gb: x4, x8, x16 DDR3 SDRAM Td0 Te0 Tf0 t DLLK SRX 2 MRS 3 MRS 4 MRS MRD ...
Page 120
... DQ BL8 DLL disable DQS, DQS# DLL off DQ BL8 DLL disable Table 71: READ Electrical Characteristics, DLL Disable Mode Parameter Access window of DQS from CK, CK# PDF: 09005aef826aa906 1Gb_DDR3_SDRAM.pdf – Rev. J 05/ NOP NOP NOP NOP ( 120 1Gb: x4, x8, x16 DDR3 SDRAM NOP NOP NOP DQSCK ( ...
Page 121
... Input Clock Frequency Change When the DDR3 SDRAM is initialized, it requires the clock to be stable during most nor- mal states of operation. This means that after the clock frequency has been set to the stable state, the clock period is not allowed to deviate except what is allowed for by the clock jitter and spread spectrum clocking (SSC) specifications ...
Page 122
... TT,nom charge power-down mode, R will remain in the off state. The ODT signal can be TT registered either LOW or HIGH in this case. 122 1Gb: x4, x8, x16 DDR3 SDRAM Input Clock Frequency Change New clock frequency Tc1 Td0 Td1 t CL ...
Page 123
... Note that nonstandard ODT schemes are required. The memory controller using the write leveling procedure must have adjustable delay settings on its DQS strobe to align the rising edge of DQS to the clock at the DRAM pins. This is accomplished when the DRAM asynchronously feeds back the CK status via the DQ bus and samples with the rising edge of DQS ...
Page 124
... Expected usage if used during write leveling: Case 1 may be used when DRAM are on a Notes: 2. Since the DRAM DQS is not being driven (MR1[12] = 1), DQS ignores the input strobe, 3. Since the DRAM DQS is being driven (MR1[12] = 0), DQS captures the input strobe, and PDF: 09005aef826aa906 1Gb_DDR3_SDRAM.pdf – ...
Page 125
... Write Leveling Procedure A memory controller initiates the DRAM write leveling mode by setting MR1[ assuming the other programable features (MR0, MR1, MR2, and MR3) are first set and the DLL is fully reset and locked. The DQ balls enter the write leveling mode going from a High-Z state to an undefined driving state, so the DQ bus should not be driven ...
Page 126
... Notes: 2. NOP: NOP or DES. 3. DQS, DQS# needs to fulfill minimum pulse width requirements 4. Differential DQS is the differential data strobe (DQS, DQS#). Timing reference points are 5. DRAM drives leveling feedback on a prime DQ (DQ0 for x4 and x8). The remaining DQ PDF: 09005aef826aa906 1Gb_DDR3_SDRAM.pdf – Rev. J 05/ ...
Page 127
... The ODT input should be deasserted LOW such that ODTL off (MIN) expires after the DQS is no longer driving LOW. When ODT LOW satisfies ~Tb0) until the DRAM is ready for either another rank to be leveled or until the normal mode can be used. After DQS termination is switched off, write level mode should be disabled via the MRS command (at Tc2) ...
Page 128
... SET command. DLLK (512) cycles of clock input are required to lock the DLL. temperature (PVT). Prior to normal operation DLLK and ZQinit have been satisfied, the DDR3 SDRAM will be ready for normal operation. 128 1Gb: x4, x8, x16 DDR3 SDRAM during power ramp DDQ ...
Page 129
... RESET# T (MIN) = 10ns CKE ODT Command DM Address A10 BA[2:0] DQS 200µs (MIN) All voltage supplies valid and stable PDF: 09005aef826aa906 1Gb_DDR3_SDRAM.pdf – Rev. J 05/10 EN Stable and VTD valid clock t CKSRX NOP MRS Code Code BA0 = L BA1 = H BA2 = 500µs (MIN) ...
Page 130
... Mode Registers Mode registers (MR0–MR3) are used to define various modes of programmable opera- tions of the DDR3 SDRAM. A mode register is programmed via the mode register set (MRS) command during initialization, and it retains the stored information (except for MR0[8] which is self-clearing) until it is either reprogrammed, RESET# goes LOW, or until the device loses power ...
Page 131
... DLL RESET, write recovery, and precharge power-down mode, as shown in Figure 53 (page 132). Burst Length Burst length is defined by MR0[1: 0]. Read and write accesses to the DDR3 SDRAM are burst-oriented, with the burst length being programmable to 4 (chop mode), 8 (fixed), or selectable using A12 during a READ/WRITE command (on-the-fly). The burst length determines the maximum number of column locations that can be accessed for a given READ or WRITE command ...
Page 132
... Reserved 132 1Gb: x4, x8, x16 DDR3 SDRAM Mode Register 0 (MR0 Address bus Mode register 0 (MR0 Burst Length 0 0 Fixed BL8 (on-the-fly via A12 Fixed BC4 (chop Reserved CAS Latency M3 READ Burst Type Reserved 0 Sequential (nibble Interleaved Micron Technology, Inc. reserves the right to change products or specifications without notice. ...
Page 133
... for BL8. t DLLK) clock cycles before a READ command can be issued. This DQSCK timings. 133 1Gb: x4, x8, x16 DDR3 SDRAM Mode Register 0 (MR0) Burst Type = Interleaved (Decimal Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2006 Micron Technology, Inc. All rights reserved. ...
Page 134
... The CL is defined by MR0[6:4], as shown in Figure 53 (page 132). CAS latency is the de- lay, in clock cycles, between the internal READ command and the availability of the first bit of output data. The CL can be set 10. DDR3 SDRAM do not support half-clock latencies. Examples and are shown below internal READ command is regis- tered at clock edge n, and the CAS latency is m clocks, the data will be available nominally coincident with clock edge ...
Page 135
... RZQ/12 (20Ω [NOM]) n RZQ/8 (30Ω [NOM]) n Reserved Reserved Reserved Reserved for use. are available for use. 135 1Gb: x4, x8, x16 DDR3 SDRAM Mode Register 1 (MR1) value (ODT), WRITE LEVELING, POSTED TT,nom t MRD and Address bus Mode register 1 (MR1 ODS AL ODS DLL TT TT ...
Page 136
... DQS, DQS#) are tri-stated. The output disable feature is intended to be used during I eling) only. TDQS Enable Termination data strobe (TDQS feature of the x8 DDR3 SDRAM configuration that provides termination resistance (R tions. TDQS is not supported x16 configurations. When enabled via the mode register (MR1[11]), the R TDQS#. In contrast to the RDQS function of DDR2 SDRAM, DDR3’ ...
Page 137
... DM function is not supported. When the TDQS function is disabled, the DM function is provided, and the TDQS# ball is not used. The TDQS function is available in the x8 DDR3 SDRAM configuration only and must be disabled via the mode register for the x4 and x16 configurations. On-Die Termination ODT resistance R termination value applies to the DQ, DM, DQS, DQS#, and TDQS, TDQS# balls ...
Page 138
... CK. The READ or WRITE command is held for the time of the AL before it is released internally to the DDR3 SDRAM device. READ latency (RL) is controlled by the sum of the AL and CAS latency (CL CL. WRITE latency (WL) is the sum of CAS WRITE latency and AL CWL (see Mode Register 2 (MR2) (page 138)). Exam- ples of READ and WRITE latencies are shown in Figure 56 (page 138) and Figure 58 (page 139) ...
Page 139
... Auto Self Refresh Dynamic ODT M10 M9 TT(WR) 0 Disabled: Manual R disabled 0 0 TT(WR) 1 Enabled: Automatic RZQ RZQ Reserved NOP NOP CWL = 11 139 1Gb: x4, x8, x16 DDR3 SDRAM Mode Register 2 (MR2) A10 SRT ASR CWL TT(WR CAS Write Latency (CWL ≥ 2.5ns (2.5ns > ≥ 1.875ns) ...
Page 140
... ASR enables the refresh rate to automatically adjust between over the supported temperature range. One other disadvantage with ASR is the DRAM cannot always switch from refresh rate at an exact case temperature of +85°C. Although the DRAM will support data integrity when it switches from refresh rate, it may switch at a lower temperature than +85° ...
Page 141
... MPR register, and bits 1 and 0 determine which mode the MPR is placed in. The basic concept of the multipurpose register is shown in Figure 60 (page 142). If MR3[ then the MPR access is disabled, and the DRAM operates in normal mode. However, if MR3[ then the DRAM no longer outputs normal read data PDF: 09005aef826aa906 1Gb_DDR3_SDRAM.pdf – ...
Page 142
... MPR contents can be read out continuously with a regular READ or RDAP command. Normal operation, no MPR transaction All subsequent READs come from the DRAM memory array All subsequent WRITEs go to the DRAM memory array Enable MPR mode, subsequent READ/RDAP commands defined by bits 1 and 2 142 1Gb: x4, x8, x16 DDR3 SDRAM ...
Page 143
... RFU n/a n/a n/a n/a n/a n/a 143 1Gb: x4, x8, x16 DDR3 SDRAM Mode Register 3 (MR3) Burst Order and Data Pattern Burst order Predefined pattern Burst order Predefined pattern Burst order Predefined pattern n/a n/a n/a n/a ...
Page 144
... Read Length A[2:0] RFU n/a n/a n/a ted MPR agent. 144 1Gb: x4, x8, x16 DDR3 SDRAM Mode Register 3 (MR3) Burst Order and Data Pattern n/a n/a n/a n/a n/a n/a Micron Technology, Inc. reserves the right to change products or specifications without notice. ...
Page 145
Figure 61: MPR System Read Calibration with BL8: Fixed Burst Order Single Readout T0 Ta0 Tb0 Tb1 CK# CK READ 1 Command PREA MRS NOP MOD Bank address 3 Valid 0 2 A[1: ...
Page 146
Figure 62: MPR System Read Calibration with BL8: Fixed Burst Order, Back-to-Back Readout Tc0 CK# CK READ 1 READ 1 Command PREA MRS t CCD MOD Bank address 3 Valid Valid ...
Page 147
Figure 63: MPR System Read Calibration with BC4: Lower Nibble, Then Upper Nibble Tc0 CK# CK READ 1 READ 1 Command PREA MRS MOD t CCD Bank address 3 Valid Valid ...
Page 148
Figure 64: MPR System Read Calibration with BC4: Upper Nibble, Then Lower Nibble Tc0 CK# CK READ 1 READ 1 Command PREA MRS MOD t CCD Bank address 3 Valid Valid ...
Page 149
... Data WRITE operations are not allowed until the MPR returns to the normal 4. Issue a read with burst order information (all other address pins are “Don’t Care”): 5. After CL, the DRAM bursts out the predefined read calibration pattern 6. The memory controller repeats the calibration reads until read data capture at 7 ...
Page 150
... All banks must be precharged and can be issued to the DRAM. No other activities (other than another ZQCL or ZQCS com- mand may be issued to another DRAM) can be performed on the DRAM channel by the controller for the duration of helps accurately calibrate R should disable the ZQ ball’s current consumption path to reduce power. ...
Page 151
... ACTIVATE Operation Before any READ or WRITE commands can be issued to a bank within the DRAM, a row in that bank must be opened (activated). This is accomplished via the ACTIVATE com- mand, which selects both the bank and the row to be activated. After a row is opened with an ACTIVATE command, a READ or WRITE command may ...
Page 152
... PDF: 09005aef826aa906 1Gb_DDR3_SDRAM.pdf – Rev. J 05/ ACT NOP ACT Row Row Bank b Bank c t FAW 152 1Gb: x4, x8, x16 DDR3 SDRAM ACTIVATE Operation T9 T10 T11 T19 NOP ACT NOP NOP Row Bank d Indicates A Break in Time Scale Micron Technology, Inc. reserves the right to change products or specifications without notice. ...
Page 153
... Notes: 2. Subsequent elements of data-out appear in the programmed order following DO n. DQS, DQS# is driven by the DRAM along with the output data. The initial low state on DQS and HIGH state on DQS# is known as the READ preamble ( on DQS and the HIGH state on DQS#, coincident with the last data-out element, is known as the READ postamble ( commands have been initiated, the DQ will go High-Z ...
Page 154
... However, the precharge period will be determined by the last PRECHARGE command issued to the bank. If A10 is HIGH when a READ command is issued, the READ with auto precharge func- tion is engaged. The DRAM starts an auto precharge operation on the rising edge, which Figure 77 (page 158)). If ...
Page 155
Figure 69: Consecutive READ Bursts (BL8 CK# CK Command 1 READ NOP NOP NOP t CCD Bank, Address 2 Col n DQS, DQS NOP commands are shown for ease of ...
Page 156
Figure 71: Nonconsecutive READ Bursts CK# CK Command READ NOP NOP NOP NOP Bank a, Address Col DQS, DQS Notes ...
Page 157
Figure 73: READ (BC4) to WRITE (BC4) OTF CK# CK Command 1 READ NOP NOP NOP READ-to-WRITE command delay = CCD Bank, Address 2 Col n DQS, ...
Page 158
Figure 75: READ to PRECHARGE (BC4 CK# CK Command READ NOP NOP NOP NOP Bank a, Address Col n t RTP DQS, DQS RAS Figure 76: READ to PRECHARGE ( ...
Page 159
... DDR3 SDRAM t DQSQ of the crossing point of DQS, DQS#. t DQSCK of the clock crossing point. The data ). Prior to data output from the DRAM, DDQ t RPRE. This is known as the READ preamble. t RPST, is one half clock from the last DQS, DQS# transition. Dur- 159 Micron Technology, Inc ...
Page 160
Figure 78: Data Output Timing – DQSQ and Data Valid Window T0 T1 CK# CK Command 1 READ NOP Bank, Address 2 Col n DQS, DQS (last data valid (first data no longer valid) All ...
Page 161
... QSH t QSL Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 t DQSCK (MAX) t DQSCK (MAX) t QSH t QSL t QSH t RPRE Bit 0 Bit 1 Bit 2 161 1Gb: x4, x8, x16 DDR3 SDRAM t HZ (DQ) or begins driving (DQS), LZ (DQ) by measur (DQS DQSCK (MIN (DQS) MIN t RPST Bit 5 Bit 6 Bit 7 ...
Page 162
... QSL. Likewise, LZ (DQS) MIN and t strobe case) and LZ (DQS) MAX and strobe case); however, they tend to track one another. mum pulse width of the READ postamble is defined RPRE begins t RPRE 162 1Gb: x4, x8, x16 DDR3 SDRAM V + 2xmV xmV (DQS (DQ xmV 2xmV (DQS (DQ) begin point = 2 × ...
Page 163
... Resulting differential signal relevant for t RPST specification PDF: 09005aef826aa906 1Gb_DDR3_SDRAM.pdf – Rev. J 05/ CK# DQS RPST begins 163 1Gb: x4, x8, x16 DDR3 SDRAM RPST RPST ends Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2006 Micron Technology, Inc. All rights reserved. ...
Page 164
... WTR and WR starting time may vary depending on the mode register settings 164 1Gb: x4, x8, x16 DDR3 SDRAM WRITE Operation t DQSS (MIN) and Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2006 Micron Technology, Inc. All rights reserved. ...
Page 165
... WPST specification PDF: 09005aef826aa906 1Gb_DDR3_SDRAM.pdf – Rev. J 05/ WPRE begins t WPRE t WPST T1 t WPST begins 165 Micron Technology, Inc. reserves the right to change products or specifications without notice. 1Gb: x4, x8, x16 DDR3 SDRAM WRITE Operation WPRE ends WPST ends ...
Page 166
... WRITE command at T0. t DQSS must be met at each rising clock edge. t WPST is usually depicted as ending at the crossing of DQS, DQS#; however, ly ends when DQS no longer drives LOW and DQS# no longer drives HIGH. 166 1Gb: x4, x8, x16 DDR3 SDRAM WRITE Operation NOP NOP ...
Page 167
Figure 86: Consecutive WRITE (BL8) to WRITE (BL8 CK# CK Command 1 WRITE NOP NOP NOP t CCD Address 2 Valid DQS, DQS NOP commands are shown for ease of ...
Page 168
Figure 88: Nonconsecutive WRITE to WRITE CK# CK Command WRITE NOP NOP NOP NOP Address Valid WL = CWL + DQS, DQS Notes ( data-in ...
Page 169
Figure 90: WRITE to READ (BC4 Mode Register Setting CK# CK Command 1 WRITE NOP NOP Address 3 Valid DQS, DQS NOP commands are shown for ease of illustration; other commands ...
Page 170
Figure 91: WRITE (BC4 OTF) to READ (BC4 OTF CK# CK Command 1 WRITE NOP NOP NOP Address 3 Valid DQS, DQS Notes: 1. NOP commands are shown for ease of ...
Page 171
... WR) is referenced from the first rising clock edge after the last t write data is shown at T7. WR specifies the last burst WRITE cycle until the PRECHARGE command can be issued to the same bank. 171 1Gb: x4, x8, x16 DDR3 SDRAM T8 T9 T10 T11 T12 NOP ...
Page 172
... The WRITE preamble and postamble are also shown here. One clock prior to data input to the DRAM, DQS must be HIGH and DQS# must be LOW. Then for a half clock, DQS is driven LOW (DQS# is driven HIGH) during the WRITE preamble, must be kept LOW by the controller after the last data is written to the DRAM during the WRITE postamble, Data setup and hold times are shown ...
Page 173
... PDF: 09005aef826aa906 1Gb_DDR3_SDRAM.pdf – Rev. J 05/ WPRE t DQSH t DQSL 173 1Gb: x4, x8, x16 DDR3 SDRAM t DH Transitioning Data Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2006 Micron Technology, Inc. All rights reserved. t WPST Don’t Care ...
Page 174
... CK specifications) when self refresh mode is entered. If the clock remains stable and the frequency is not altered while in self refresh mode, then the DRAM is allowed to exit self refresh mode after later than when CKE was registered LOW). Since the clock remains stable in self refresh ...
Page 175
... XS is required before any commands not requiring a locked DLL. t XSDLL is required before any commands requiring a locked DLL. example, all banks must be precharged, progress. clock edge where CKE HIGH satisfies t ISXR is satisfied at Tc1. 175 1Gb: x4, x8, x16 DDR3 SDRAM SELF REFRESH Operation Tc0 Tc1 Td0 t CKSRX NOP 5 ...
Page 176
... Micron’s DDR3 SDRAM supports the optional extended temperature range of 0°C to +95°C, T The extended temperature range DRAM must be refreshed externally at 2X (double re- fresh) anytime the case temperature is above +85°C (and does not exceed +95°C). The external refreshing requirement is accomplished by reducing the refresh period from 64ms to 32ms ...
Page 177
... During power-down entry, if any bank remains open after all in-progress commands are complete, the DRAM will be in active power-down mode. If all banks are closed af- ter all in-progress commands are complete, the DRAM will be in precharge power- down mode. Precharge power-down mode must be programmed to exit with either a slow exit mode or a fast exit mode ...
Page 178
... While in either power-down state, CKE is held LOW, RESET# is held HIGH, and a stable clock signal must be maintained. ODT must valid state but all other input signals are a “Don’t Care.” If RESET# goes LOW during power-down, the DRAM will switch out of power-down mode and go into the reset state. After CKE is registered LOW, CKE ...
Page 179
... Valid Enter power-down mode PDF: 09005aef826aa906 1Gb_DDR3_SDRAM.pdf – Rev. J 05/ Ta0 t CL NOP CPDED Exit power-down 179 1Gb: x4, x8, x16 DDR3 SDRAM Power-Down Mode Ta1 Ta2 Ta3 NOP NOP NOP CKE (MIN mode Indicates A Break in Time Scale Micron Technology, Inc. reserves the right to change products or specifications without notice. ...
Page 180
... Any valid command requiring a locked DLL. PDF: 09005aef826aa906 1Gb_DDR3_SDRAM.pdf – Rev. J 05/ NOP t CPDED Exit power-down NOP t CPDED Exit power-down 180 1Gb: x4, x8, x16 DDR3 SDRAM Power-Down Mode T4 T5 Ta0 NOP NOP NOP t CKE (MIN mode Indicates A Break in Time Scale T4 Ta Ta1 Valid 1 NOP NOP ...
Page 181
... WRPDEN t CK earlier if BC4MRS. 181 Micron Technology, Inc. reserves the right to change products or specifications without notice. 1Gb: x4, x8, x16 DDR3 SDRAM Power-Down Mode Ta7 Ta8 Ta9 Ta10 NOP NOP CPDED t PD Power-down or self refresh entry Indicates A Break In Transitioning Data Time Scale ...
Page 182
... WR is programmed through MR0[11:9] and represents t the next integer CK earlier if BC4MRS NOP NOP t CPDED RFC, CKE must remain HIGH until 182 1Gb: x4, x8, x16 DDR3 SDRAM Power-Down Mode Ta6 Ta7 Tb0 Tb1 NOP NOP NOP NOP CPDED Start internal Power-down or self refresh entry 2 ...
Page 183
... CL NOP NOP t CPDED NOP NOP t CPDED t IS 183 Micron Technology, Inc. reserves the right to change products or specifications without notice. 1Gb: x4, x8, x16 DDR3 SDRAM Power-Down Mode © 2006 Micron Technology, Inc. All rights reserved. T7 Don’t Care T7 Don’t Care ...
Page 184
... NOP t CPDED Exit power-down t XP must be satisfied before issuing the command. t XPDLL must be satisfied (referenced to the registration of power-down exit) before the next power-down can be entered. 184 1Gb: x4, x8, x16 DDR3 SDRAM Power-Down Mode Ta1 Ta2 Ta3 t CPDED NOP NOP Indicates A Break in ...
Page 185
... LOW, and there are no restrictions about when it can go LOW. After RESET# goes LOW, it must remain LOW for 100ns. During this time, the outputs are disabled, ODT (R turns off (High-Z), and the DRAM resets itself. CKE should be brought LOW prior to RE- SET# being driven HIGH. After RESET# goes HIGH, the DRAM must be reinitialized as though a normal power-up was executed ...
Page 186
... A10 BA[2:0] High-Z DQS High-Z DQ High 500µs (MIN) All voltage supplies valid and stable 1. The minimum time required is the larger of 10ns or 5 clocks. Note: PDF: 09005aef826aa906 1Gb_DDR3_SDRAM.pdf – Rev. J 05/ MRS MRS NOP Code Code Code Code BA0 = L BA0 = H BA1 = H ...
Page 187
... On-Die Termination (ODT) ODT is a feature that enables the DRAM to enable/disable and turn on/off termination resistance for each DQ, DQS, DQS#, and DM for the x4 and x8 configurations (and TDQS, TDQS# for the x8 configuration, when enabled). ODT is applied to each DQ, UDQS, UDQS#, LDQS, LDQS#, UDM, and LDM signal for the x16 configuration. ...
Page 188
... Definition. The R mentioned. DDR3 SDRAM supports multiple R can and RZQ is 240Ω. R the DRAM is initialized, calibrated, and not performing read access or when it is not in self refresh mode. Write accesses use R ing writes, only RZQ/2, RZQ/4, and RZQ/6 are allowed (see Table 83 (page 190)). ODT timings are summarized in Table 81 (page 188), as well as listed in Table 54 (page 76) ...
Page 189
... Dynamic ODT In certain application cases, and to further enhance signal integrity on the data bus desirable that the termination strength of the DDR3 SDRAM can be changed without issuing an MRS command, essentially changing the ODT termination on the fly. With dynamic ODT (R dynamic ODT (R to nominal ODT (R supported by the dynamic ODT feature, as described below ...
Page 190
... Reserved is used during WRITEs, only RZQ/2, RZQ/4, RZQ/6 are allowed. TT,nom TT(WR) R (RZQ) TT(WR) Dynamic ODT off: WRITE does not affect R RZQ/4 RZQ/2 Reserved 190 1Gb: x4, x8, x16 DDR3 SDRAM Dynamic ODT (Ohms) R Mode Restriction TT,nom TT,nom Off 60 Self refresh 120 40 ...
Page 191
Figure 110: Dynamic ODT: ODT Asserted Before and After the WRITE, BC4 CK# CK Command NOP NOP NOP NOP WRS4 NOP Address Valid ODTH4 ODT ODTL on t AON (MIN AON ...
Page 192
Figure 112: Dynamic ODT: ODT Pin Asserted Together with WRITE Command for 6 Clock Cycles, BL8 CK# CK NOP WRS8 NOP Command ODTL cnw Address Valid ODTL on ODT R TT DQS, DQS Via MRS ...
Page 193
... WL ODTH4 is satisfied. ODT registered LOW also legal NOP NOP NOP cnw ODTH4 t ADC (MAX AON (MIN) ODTL 4 cwn WL ODT can remain HIGH enabled. TT(WR) 193 1Gb: x4, x8, x16 DDR3 SDRAM NOP NOP NOP ODTL off t ADC (MIN) R TT,nom t ADC (MAX Transitioning and R are enabled ...
Page 194
... ODTL off. When ODT is asserted, it must remain HIGH until ODTH4 is satisfied WRITE com- mand is registered by the DRAM with ODT HIGH, then ODT must remain HIGH until ODTH4 (BC4) or ODTH8 (BL8) after the WRITE command (see Figure 116 (page 196)). ODTH4 and ODTH8 are measured from ODT registered HIGH to ODT registered LOW or from the registration of a WRITE command until ODT is registered LOW ...
Page 195
Table 86: Synchronous ODT Parameters Symbol Description ODTL on ODT synchronous turn-on delay ODTL off ODT synchronous turn-off delay ODTH4 ODT minimum HIGH time after ODT assertion or WRITE (BC4) ODTH8 ODT minimum HIGH time after WRITE (BL8) t AON ...
Page 196
Figure 116: Synchronous ODT (BC4 CK# CK CKE Command NOP NOP NOP NOP NOP ODTH4 ODT ODTL Notes: TT,nom 2. ODT must be ...
Page 197
... Rev. J 05/ enabled). R TT,nom TT(WR) TT 197 Micron Technology, Inc. reserves the right to change products or specifications without notice. 1Gb: x4, x8, x16 DDR3 SDRAM must be disabled TT may not be enabled until the end of the post- © 2006 Micron Technology, Inc. All rights reserved. ...
Page 198
Figure 117: ODT During READs CK# CK Command READ NOP NOP NOP NOP Address Valid ODTL off = CWL + ODT DQS, DQS# DQ Note: 1. ODT must be ...
Page 199
... Asynchronous ODT Mode Asynchronous ODT mode is available when the DRAM runs in DLL on mode and when either R charged power-down standby (via MR0[12]). Additionally, ODT operates asynchronous- ly when the DLL is synchronizing after being reset. See Power-Down Mode (page 177) for definition and guidance over power-down details. ...
Page 200
Figure 118: Asynchronous ODT Timing with Fast ODT Transition CK# CK CKE ODT t AONPD (MIN Note ignored. Table 87: Asynchronous ODT Timing Parameters for All ...