MT41J64M16LA-187E:B Micron Technology Inc, MT41J64M16LA-187E:B Datasheet - Page 8

• Manufacturer Part Number: MT41J64M16LA-187E:B
• Manufacturer: Micron Technology Inc
• Type: DDR3 SDRAMr

Specifications of MT41J64M16LA-187E:B

• Organization: 64Mx16
• Density: 1Gb
• Address Bus: 16b
• Maximum Clock Rate: 1.066GHz
• Operating Supply Voltage (typ): 1.5V
• Package Type: FBGA
• Operating Temp Range: 0C to 95C
• Operating Supply Voltage (max): 1.575V
• Operating Supply Voltage (min): 1.425V
• Supply Current: 265mA
• Pin Count: 96
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Compliant

List of Figures
Figure 1: DDR3 Part Numbers ......................................................................................................................... 2
Figure 2: Simplified State Diagram ................................................................................................................. 11
Figure 3: 256 Meg x 4 Functional Block Diagram ............................................................................................. 14
Figure 4: 128 Meg x 8 Functional Block Diagram ............................................................................................. 15
Figure 5: 64 Meg x 16 Functional Block Diagram ............................................................................................. 15
Figure 6: 78-Ball FBGA – x4, x8 (Top View) ...................................................................................................... 16
Figure 7: 86-Ball FBGA – x4, x8 (Top View) ...................................................................................................... 17
Figure 8: 96-Ball FBGA – x16 (Top View) ......................................................................................................... 18
Figure 9: 78-Ball FBGA – x4, x8 (JP) ................................................................................................................. 25
Figure 10: 78-Ball FBGA – x4, x8 (HX) ............................................................................................................. 26
Figure 11: 86-Ball FBGA – x4, x8 (BY) .............................................................................................................. 27
Figure 12: 96-Ball FBGA – x16 (LA) ................................................................................................................. 28
Figure 13: 96-Ball FBGA – x16 (JT) .................................................................................................................. 29
Figure 14: Thermal Measurement Point ......................................................................................................... 32
Figure 15: Input Signal .................................................................................................................................. 48
Figure 16: Overshoot ..................................................................................................................................... 49
Figure 17: Undershoot .................................................................................................................................. 49
Figure 18: V
Figure 19: Single-Ended Requirements for Differential Signals ........................................................................ 51
Figure 20: Definition of Differential AC-Swing and
Figure 21: Nominal Slew Rate Definition for Single-Ended Input Signals ......................................................... 53
Figure 22: Nominal Differential Input Slew Rate Definition for DQS, DQS# and CK, CK# .................................. 54
Figure 23: ODT Levels and I-V Characteristics ................................................................................................ 55
Figure 24: ODT Timing Reference Load .......................................................................................................... 58
Figure 25:
Figure 26:
Figure 27:
Figure 28: Output Driver ............................................................................................................................... 61
Figure 29: DQ Output Signal .......................................................................................................................... 68
Figure 30: Differential Output Signal .............................................................................................................. 69
Figure 31: Reference Output Load for AC Timing and Output Slew Rate .......................................................... 69
Figure 32: Nominal Slew Rate Definition for Single-Ended Output Signals ....................................................... 70
Figure 33: Nominal Differential Output Slew Rate Definition for DQS, DQS# ................................................... 71
Figure 34: Nominal Slew Rate and
Figure 35: Nominal Slew Rate for
Figure 36: Tangent Line for
Figure 37: Tangent Line for
Figure 38: Nominal Slew Rate and
Figure 39: Nominal Slew Rate for
Figure 40: Tangent Line for
Figure 41: Tangent Line for
Figure 42: Refresh Mode ............................................................................................................................... 116
Figure 43: DLL Enable Mode to DLL Disable Mode ........................................................................................ 118
Figure 44: DLL Disable Mode to DLL Enable Mode ........................................................................................ 119
Figure 45: DLL Disable
Figure 46: Change Frequency During Precharge Power-Down ....................................................................... 122
Figure 47: Write Leveling Concept ................................................................................................................ 123
Figure 48: Write Leveling Sequence ............................................................................................................... 126
Figure 49: Exit Write Leveling ....................................................................................................................... 127
Figure 50: Initialization Sequence ................................................................................................................. 129
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf – Rev. J 05/10 EN
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AON and
AONPD and
ADC Definition ............................................................................................................................. 60
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for Differential Signals .............................................................................................................. 50
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AOF Definitions ............................................................................................................ 59
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DQSCK Timing ........................................................................................................ 120
AOFPD Definitions ................................................................................................... 59
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IS (Command and Address – Clock) .................................................................... 101
IH (Command and Address – Clock) ................................................................... 102
DS (DQ – Strobe) ............................................................................................... 108
DH (DQ – Strobe) ............................................................................................... 109
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IH (Command and Address – Clock) .......................................................... 100
DH (DQ – Strobe) ...................................................................................... 107
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VAC for
VAC for
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IS (Command and Address – Clock) .............................................. 99
DS (DQ – Strobe) ........................................................................ 106
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DVAC ............................................................................... 51
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1Gb: x4, x8, x16 DDR3 SDRAM
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