MT41J64M16LA-187E:B Micron Technology Inc, MT41J64M16LA-187E:B Datasheet - Page 67

• Manufacturer Part Number: MT41J64M16LA-187E:B
• Manufacturer: Micron Technology Inc
• Type: DDR3 SDRAMr

Specifications of MT41J64M16LA-187E:B

• Organization: 64Mx16
• Density: 1Gb
• Address Bus: 16b
• Maximum Clock Rate: 1.066GHz
• Operating Supply Voltage (typ): 1.5V
• Package Type: FBGA
• Operating Temp Range: 0C to 95C
• Operating Supply Voltage (max): 1.575V
• Operating Supply Voltage (min): 1.425V
• Supply Current: 265mA
• Pin Count: 96
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Compliant

Output Characteristics and Operating Conditions
Table 46: Single-Ended Output Driver Characteristics
All voltages are referenced to V
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf – Rev. J 05/10 EN
Parameter/Condition
Output leakage current: DQ are disabled;
0V ≤ V
Output slew rate: Single-ended; For rising and falling edges,
measure between V
V
Single-ended DC high-level output voltage
Single-ended DC mid-point level output voltage
Single-ended DC low-level output voltage
Single-ended AC high-level output voltage
Single-ended AC low-level output voltage
Delta Ron between pull-up and pull-down for DQ/DQS
Test load for AC timing and output slew rates
REF
+ 0.1 × V
OUT
≤ V
DDQ
DDQ
; ODT is disabled; ODT is HIGH
OL(AC)
Notes:
= V
The DRAM uses both single-ended and differential output drivers. The single-ended out-
put driver is summarized below, while the differential output driver is summarized in
Table 46 while the differential output driver is summarized in Table 47 (page 68).
REF
1. RZQ of 240Ω (±1%) with RZQ/7 enabled (default 34Ω driver) and is applicable after prop-
2. V
3. See Figure 31 (page 69) for the test load configuration.
4. The 6 V/ns maximum is applicable for a single DQ signal when it is switching either from
5. See Table 36 (page 62) for IV curve linearity. Do not use AC test load.
6. See Table 48 (page 70) for output slew rate.
7. See Table 36 (page 62) for additional information.
8. See Figure 29 (page 68) for an example of a single-ended output signal.
SS
- 0.1 × V
er ZQ calibration has been performed at a stable temperature and voltage (V
V
HIGH to LOW or LOW to HIGH while the remaining DQ signals in the same byte lane are
either all static or all switching the opposite direction. For all other DQ signal switching
combinations, the maximum limit of 6 V/ns is reduced to 5 V/ns.
SSQ
TT
= V
= V
DDQ
DDQ
SS
).
/2.
and V
Output Characteristics and Operating Conditions
OH(AC)
=
67
Symbol
MM
V
V
V
V
V
SRQse
OM(DC)
OH(DC)
OH(AC)
OL(DC)
OL(AC)
I
Output to V
OZ
PUPD
Micron Technology, Inc. reserves the right to change products or specifications without notice.
1Gb: x4, x8, x16 DDR3 SDRAM
TT
Min
–10
2.5
–5
V
V
(V
TT
TT
DDQ
0.8 × V
0.5 × V
0.2 × V
+ 0.1 × V
- 0.1 × V
/2) via 25Ω resistor
DDQ
DDQ
DDQ
DDQ
DDQ
© 2006 Micron Technology, Inc. All rights reserved.
Max
+10
+5
6
Units
V/ns
µA
%
V
V
V
V
V
DDQ
1, 2, 3, 4
1, 2, 3, 6
1, 2, 3, 6
Notes
1, 2, 5
1, 2, 5
1, 2, 5
= V
1, 7
1
3
DD
,