MT41J64M16LA-187E:B Micron Technology Inc, MT41J64M16LA-187E:B Datasheet - Page 177

• Manufacturer Part Number: MT41J64M16LA-187E:B
• Manufacturer: Micron Technology Inc
• Type: DDR3 SDRAMr

Specifications of MT41J64M16LA-187E:B

• Organization: 64Mx16
• Density: 1Gb
• Address Bus: 16b
• Maximum Clock Rate: 1.066GHz
• Operating Supply Voltage (typ): 1.5V
• Package Type: FBGA
• Operating Temp Range: 0C to 95C
• Operating Supply Voltage (max): 1.575V
• Operating Supply Voltage (min): 1.425V
• Supply Current: 265mA
• Pin Count: 96
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Compliant

Power-Down Mode
Table 78: Command to Power-Down Entry Parameters
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf – Rev. J 05/10 EN
DRAM Status
Idle or active
Idle or active
Power-down
Active
Active
Active
Active
Active
Idle
Idle
WRITEAP: BL8OTF, BL8MRS,
Last Command Prior to
WRITE: BL8OTF, BL8MRS,
MODE REGISTER SET
WRITEAP: BC4MRS
Note:
READ or READAP
WRITE: BC4MRS
PRECHARGE
CKE LOW
ACTIVATE
REFRESH
REFRESH
BC4OTF
BC4OTF
Power-down is synchronously entered when CKE is registered LOW coincident with a
NOP or DES command. CKE is not allowed to go LOW while either an MRS, MPR,
ZQCAL, READ, or WRITE operation is in progress. CKE is allowed to go LOW while any
of the other legal operations (such as ROW ACTIVATION, PRECHARGE, auto precharge,
or REFRESH) are in progress. However, the power-down I
cable until such operations have been completed. Depending on the previous DRAM
state and the command issued prior to CKE going LOW, certain timing constraints must
be satisfied (as noted in Table 78). Timing diagrams detailing the different power-down
mode entry and exits are shown in Figure 97 (page 179) through Figure 106 (page 184).
Entering power-down disables the input and output buffers, excluding CK, CK#, ODT,
CKE, and RESET#. NOP or DES commands are required until
fied, at which time all specified input/output buffers will be disabled. The DLL should
be in a locked state when power-down is entered for the fastest power-down exit tim-
ing. If the DLL is not locked during power-down entry, the DLL must be reset after
exiting power-down mode for proper READ operation as well as synchronous ODT op-
eration.
During power-down entry, if any bank remains open after all in-progress commands
are complete, the DRAM will be in active power-down mode. If all banks are closed af-
ter all in-progress commands are complete, the DRAM will be in precharge power-
down mode. Precharge power-down mode must be programmed to exit with either a
slow exit mode or a fast exit mode. When entering precharge power-down mode, the
DLL is turned off in slow exit mode or kept on in fast exit mode.
The DLL remains on when entering active power-down as well. ODT has special timing
constraints when slow exit mode precharge power-down is enabled and entered. Refer
to Asynchronous ODT Mode (page 199) for detailed ODT usage requirements in slow
1. If slow-exit mode precharge power-down is enabled and entered, ODT becomes asyn-
chronous
t
XPDLL after CKE goes HIGH.
1
t
ANPD prior to CKE going LOW and remains asynchronous until
Parameter (Min)
t
t
t
WRAPDEN
t
t
MRSPDEN
ACTPDEN
t
t
WRPDEN
REFPDEN
RDPDEN
PRPDEN
t
XPDLL
177
Greater of 10
WL + 4
WL + 2
Micron Technology, Inc. reserves the right to change products or specifications without notice.
WL + 4
WL + 2
Parameter Value
RL + 4
t
t
CK + WR + 1
CK + WR + 1
t
t
t
CK +
CK +
1Gb: x4, x8, x16 DDR3 SDRAM
1
1
1
MOD
t
CK + 1
t
t
t
CK
CK
CK
t
CK or 24ns
t
t
WR/
WR/
t
CK
t
t
CK
CK
t
t
DD
CK
CK
specifications are not appli-
t
Power-Down Mode
© 2006 Micron Technology, Inc. All rights reserved.
CPDED has been satis-
Figure 104 (page 183)
Figure 105 (page 183)
Figure 100 (page 181)
Figure 101 (page 181)
Figure 101 (page 181)
Figure 102 (page 182)
Figure 102 (page 182)
Figure 103 (page 182)
Figure 107 (page 184)
Figure 106 (page 184)
Figure
t
ANPD +