MT41J64M16LA-187E:B Micron Technology Inc, MT41J64M16LA-187E:B Datasheet - Page 10

• Manufacturer Part Number: MT41J64M16LA-187E:B
• Manufacturer: Micron Technology Inc
• Type: DDR3 SDRAMr

Specifications of MT41J64M16LA-187E:B

• Organization: 64Mx16
• Density: 1Gb
• Address Bus: 16b
• Maximum Clock Rate: 1.066GHz
• Operating Supply Voltage (typ): 1.5V
• Package Type: FBGA
• Operating Temp Range: 0C to 95C
• Operating Supply Voltage (max): 1.575V
• Operating Supply Voltage (min): 1.425V
• Supply Current: 265mA
• Pin Count: 96
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Compliant

1Gb: x4, x8, x16 DDR3 SDRAM
Figure 103: REFRESH to Power-Down Entry .................................................................................................. 182
Figure 104: ACTIVATE to Power-Down Entry ................................................................................................ 183
Figure 105: PRECHARGE to Power-Down Entry ............................................................................................. 183
Figure 106: MRS Command to Power-Down Entry ........................................................................................ 184
Figure 107: Power-Down Exit to Refresh to Power-Down Entry ...................................................................... 184
Figure 108: RESET Sequence ........................................................................................................................ 186
Figure 109: On-Die Termination ................................................................................................................... 187
Figure 110: Dynamic ODT: ODT Asserted Before and After the WRITE, BC4 .................................................... 191
Figure 111: Dynamic ODT: Without WRITE Command .................................................................................. 191
Figure 112: Dynamic ODT: ODT Pin Asserted Together with WRITE Command for 6 Clock Cycles, BL8 ........... 192
Figure 113: Dynamic ODT: ODT Pin Asserted with WRITE Command for 6 Clock Cycles, BC4 ......................... 193
Figure 114: Dynamic ODT: ODT Pin Asserted with WRITE Command for 4 Clock Cycles, BC4 ......................... 193
Figure 115: Synchronous ODT ...................................................................................................................... 195
Figure 116: Synchronous ODT (BC4) ............................................................................................................. 196
Figure 117: ODT During READs .................................................................................................................... 198
Figure 118: Asynchronous ODT Timing with Fast ODT Transition .................................................................. 200
Figure 119: Synchronous to Asynchronous Transition During Precharge Power-Down (DLL Off) Entry ........... 202
Figure 120: Asynchronous to Synchronous Transition During Precharge Power-Down (DLL Off) Exit .............. 204
Figure 121: Transition Period for Short CKE LOW Cycles with Entry and Exit Period Overlapping .................... 206
Figure 122: Transition Period for Short CKE HIGH Cycles with Entry and Exit Period Overlapping ................... 207
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1Gb_DDR3_SDRAM.pdf – Rev. J 05/10 EN
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