MT41J64M16LA-187E:B TR Micron Technology Inc, MT41J64M16LA-187E:B TR Datasheet
MT41J64M16LA-187E:B TR
Specifications of MT41J64M16LA-187E:B TR
Related parts for MT41J64M16LA-187E:B TR
MT41J64M16LA-187E:B TR Summary of contents
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DDR3 SDRAM MT41J256M4 – 32 Meg banks MT41J128M8 – 16 Meg banks MT41J64M16 – 8 Meg banks Features • +1.5V ±0.075V DD DDQ • ...
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Backward compatible to 1066 (-187). Table 2: Addressing Parameter Configuration Refresh count Row addressing Bank addressing Column addressing Figure 1: DDR3 Part Numbers MT41J Configuration 256 Meg x 4 128 Meg Meg x ...
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Contents State Diagram ................................................................................................................................................ 11 Functional Description ................................................................................................................................... 12 Industrial Temperature .............................................................................................................................. 12 Automotive Temperature ........................................................................................................................... 12 General Notes ............................................................................................................................................ 13 Functional Block Diagrams ............................................................................................................................. 14 Ball Assignments and Descriptions ................................................................................................................. 16 Package Dimensions ...................................................................................................................................... 25 Electrical Specifications .................................................................................................................................. 30 ...
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DLL Disable Mode ..................................................................................................................................... 117 Input Clock Frequency Change ...................................................................................................................... 121 Write Leveling ............................................................................................................................................... 123 Write Leveling Procedure ........................................................................................................................... 125 Write Leveling Mode Exit Procedure ........................................................................................................... 127 Initialization ................................................................................................................................................. 128 Mode Registers .............................................................................................................................................. 130 Mode Register 0 (MR0) .................................................................................................................................. 131 ...
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ODT Off During READs .............................................................................................................................. 197 Asynchronous ODT Mode .............................................................................................................................. 199 Synchronous to Asynchronous ODT Mode Transition (Power-Down Entry) ................................................. 201 Asynchronous to Synchronous ODT Mode Transition (Power-Down Exit) ....................................................... 203 Asynchronous to Synchronous ODT Mode Transition (Short CKE Pulse) ...
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List of Tables Table 1: Key Timing Parameters ...................................................................................................................... 1 Table 2: Addressing ......................................................................................................................................... 2 Table 3: 78-Ball FBGA – x4, x8 Ball Descriptions .............................................................................................. 19 Table 4: 86-Ball FBGA – x4, x8 Ball Descriptions .............................................................................................. 21 Table 5: 96-Ball ...
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Table 51: DDR3-1333 Speed Bins ................................................................................................................... 73 Table 52: DDR3-1600 Speed Bins ................................................................................................................... 74 Table 53: DDR3-1866 Speed Bins ................................................................................................................... 75 Table 54: Electrical Characteristics and AC Operating Conditions ................................................................... 76 Table 55: Electrical Characteristics and AC Operating Conditions for ...
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List of Figures Figure 1: DDR3 Part Numbers ......................................................................................................................... 2 Figure 2: Simplified State Diagram ................................................................................................................. 11 Figure 3: 256 Meg x 4 Functional Block Diagram ............................................................................................. 14 Figure 4: 128 Meg x 8 Functional Block Diagram ............................................................................................. 15 Figure ...
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Figure 51: MRS to MRS Command Timing ( Figure 52: MRS to nonMRS Command Timing ( Figure 53: Mode Register 0 (MR0) Definitions ................................................................................................ 132 Figure 54: READ Latency .............................................................................................................................. 134 Figure 55: Mode Register 1 (MR1) Definition ................................................................................................. 135 ...
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Figure 103: REFRESH to Power-Down Entry .................................................................................................. 182 Figure 104: ACTIVATE to Power-Down Entry ................................................................................................ 183 Figure 105: PRECHARGE to Power-Down Entry ............................................................................................. 183 Figure 106: MRS Command to Power-Down Entry ........................................................................................ 184 Figure 107: Power-Down Exit to Refresh to ...
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State Diagram Figure 2: Simplified State Diagram Power applied Reset Power procedure on From any RESET state ACT = ACTIVATE MPR = Multipurpose register MRS = Mode register set PDE = Power-down entry PDX = Power-down exit PRE = PRECHARGE ...
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Functional Description DDR3 SDRAM uses a double data rate architecture to achieve high-speed operation. The double data rate architecture is an 8n-prefetch architecture with an interface de- signed to transfer two data words per clock cycle at the I/O pins. ...
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General Notes • The functionality and the timing specifications discussed in this data sheet are for the DLL enable mode of operation (normal operation). • Throughout this data sheet, various figures and text refer to DQs as “DQ.” DQ term ...
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... Functional Block Diagrams DDR3 SDRAM is a high-speed, CMOS dynamic random access memory internally configured as an 8-bank DRAM. Figure 3: 256 Meg x 4 Functional Block Diagram ODT ZQ RZQ RESET# ZQCL, ZQCS CKE Control V SSQ logic A12 CK, CK# BC4 (burst chop) CS# RAS# OTF CAS# ...
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... Bank 7 Bank 7 Bank 6 Bank 6 Bank 5 Bank 5 Bank 4 Bank 4 Bank 3 Bank 3 Bank 2 Bank 2 Bank 1 Bank 1 Bank 0 Bank 0 Row- 13 memory row- array address MUX 8,192 (8192 x 128 x 128) latch and decoder Sense amplifiers 128 16,384 BC4 OTF I/O gating DM mask logic Bank control ...
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Ball Assignments and Descriptions Figure 6: 78-Ball FBGA – x4, x8 (Top View Notes: 1. Ball descriptions listed in Table 3 (page 19) are listed as “x4, ...
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Figure 7: 86-Ball FBGA – x4, x8 (Top View Ball descriptions listed in Table 4 (page 21) are listed as ...
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Figure 8: 96-Ball FBGA – x16 (Top View Ball descriptions listed in Table 5 (page 23) are listed as “x4, x8” if unique; ...
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... Address inputs: Provide the row address for ACTIVATE commands, and the column address and auto precharge bit (A10) for READ/WRITE commands, to select one location out of the memory array in the respective bank. A10 sampled during a PRECHARGE command determines whether the PRECHARGE applies to one bank (A10 LOW, bank selected by BA[2:0]) or all banks (A10 HIGH) ...
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Table 3: 78-Ball FBGA – x4, x8 Ball Descriptions (Continued) Symbol Type DQ0, DQ1, DQ2, I/O DQ3, DQ4, DQ5, DQ6, DQ7 DQS, DQS# I/O TDQS, TDQS# Output V Supply DD V Supply DDQ V Supply REFCA V Supply REFDQ V ...
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... Address inputs: Provide the row address for ACTIVATE commands, and the column address and auto precharge bit (A10) for READ/WRITE commands, to select one location out of the memory array in the respective bank. A10 sampled during a PRECHARGE command determines whether the PRECHARGE applies to one bank (A10 LOW, bank selected by BA[2:0]) or all banks (A10 HIGH) ...
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Table 4: 86-Ball FBGA – x4, x8 Ball Descriptions (Continued) Symbol Type DQ0, DQ1, DQ2, I/O DQ3, DQ4, DQ5, DQ6, DQ7 DQS, DQS# I/O TDQS, TDQS# Output V Supply DD V Supply DDQ V Supply REFCA V Supply REFDQ V ...
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... Address inputs: Provide the row address for ACTIVATE commands, and the column address and auto precharge bit (A10) for READ/WRITE commands, to select one location out of the memory array in the respective bank. A10 sampled during a PRECHARGE command determines whether the PRECHARGE applies to one bank (A10 LOW, bank selected by BA[2:0]) or all banks (A10 HIGH) ...
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Table 5: 96-Ball FBGA – x16 Ball Descriptions (Continued) Symbol Type UDM Input DQ0, DQ1, DQ2, I/O DQ3, DQ4, DQ5, DQ6, DQ7 DQ8, DQ9, DQ10, I/O DQ11, DQ12, DQ13, DQ14, DQ15 LDQS, LDQS# I/O UDQS, UDQS# I/O V Supply DD ...
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Package Dimensions Figure 9: 78-Ball FBGA – x4, x8 (JP) Seating plane 0. 78X Ø0.45 Solder ball material: SAC305. Dimensions apply to solder balls post reflow on Ø0.35 SMD ball pads. 0.8 TYP 9.6 CTR ...
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Figure 10: 78-Ball FBGA – x4, x8 (HX) Seating plane A 0.12 A 78X Ø0.45 Solder ball material: SAC305. Dimensions apply to solder balls post reflow on Ø0.33 NSMD ball pads. 9.6 CTR 0.8 TYP 0.8 TYP ...
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Figure 11: 86-Ball FBGA – x4, x8 (BY) Seating plane A 0.12 A 86X Ø0.45 Solder ball material: SAC305. Dimensions apply to solder balls post-reflow on Ø0.33 NSMD ball pads. 0.8 TYP 14.4 CTR 2.4 0.8 TYP ...
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Figure 12: 96-Ball FBGA – x16 (LA) Seating plane A 0.12 A 96X Ø0.45 Solder ball material: SAC305. Dimensions apply to solder balls post-reflow on Ø0.33 NSMD ball pads. 12 CTR 0.8 TYP 0.8 TYP 6.4 CTR ...
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Figure 13: 96-Ball FBGA – x16 (JT) Seating plane 0. 96X Ø0.45 Solder ball material: SAC305 (96.5% Sn, 3% Ag, 0.5% Cu). Dimensions apply solder balls post-reflow on Ø0.35 SMD ball pads. 12 CTR ...
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Electrical Specifications Absolute Ratings Stresses greater than those listed in Table 6 may cause permanent damage to the de- vice. This is a stress rating only, and functional operation of the device at these or any other conditions outside those ...
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Input/Output Capacitance Table 7: Input/Output Capacitance Note 1 applies to the entire table Capacitance Parameters Symbol CK and CK Δ CK# C DCK Single-end I/O: DQ Differential I/O: DQS, C DQS#, TDQS, TDQS# ΔC: ...
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Thermal Characteristics Table 8: Thermal Characteristics Parameter/Condition Operating case temperature Junction-to-case (TOP) Notes: 1. MAX operating case temperature thermal solution must be designed to ensure the DRAM device does not exceed the 3. Device functionality is not ...
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Electrical Specifications – I Within the following I are used, unless stated otherwise: • LOW: V • Midlevel: Inputs are V • • R TT,nom • R TT(WR) • Qoff is enabled in MR1 • ODT is enabled ...
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Table 10: I Measurement Loop DD0 nRAS 0 nRC nRC + 1 nRC + 2 nRC + 3 nRC + 4 nRC + nRAS 1 2 × nRC 2 4 × nRC 3 6 × ...
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Table 11: I Measurement Loop DD1 nRCD nRAS 0 nRC nRC + 1 nRC + 2 nRC + 3 nRC + 4 nRC + nRCD nRC + nRAS 1 2 × nRC 2 4 × ...
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Table 12: I Measurement Conditions for Power-Down Currents DD I DD2P0 Power-Down Name Current (Slow Exit) Timing pattern CKE External clock RAS t RCD t RRD CS# Command inputs Row/column ...
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Table 13: I and I Measurement Loop DD2N DD3N 4–7 2 8–11 3 12–15 4 16–19 5 20–23 6 24–27 7 28–31 1. DQ, DQS, DQS# are midlevel. Notes LOW. 3. ...
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Table 15: I Measurement Loop DD4R 8–15 2 16–23 3 24–31 4 32–39 5 40–47 6 48–55 7 56–63 1. DQ, DQS, DQS# are midlevel when not driving in burst ...
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Table 16: I Measurement Loop DD4W 8–15 2 16–23 3 24–31 4 32–39 5 40–47 6 48–55 7 56–63 1. DQ, DQS, DQS# are midlevel when not driving in burst ...
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Table 17: I Measurement Loop DD5B 5–8 1c 9–12 1d 13–16 1e 17–20 1f 21–24 1g 25–28 1h 29–32 2 33–nRFC - 1 1. DQ, DQS, DQS# are midlevel. Notes ...
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Table 18: I Measurement Conditions for DD6 Normal Temperature Range I Test DD CKE External clock Off, CK and CK# = LOW RAS t RCD t RRD CS# ...
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Table 19: I Measurement Loop DD7 nRRD nRRD + 1 1 nRRD + 2 nRRD + × nRRD 3 3 × nRRD 4 × nRRD 4 4 × nRRD + 1 5 ...
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Table 19: I Measurement Loop (Continued) DD7 16 3 × nFAW + nRRD 17 3 × nFAW + 2 × nRRD 18 3 × nFAW + 3 × nRRD 3 × nFAW + 4 × nRRD 19 3 × nFAW ...
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Electrical Characteristics – values are for full operating range of voltage and temperature unless otherwise noted. DD Table 20: I Maximum Limits DD Speed Bin I Width DDR3-800 DD0 x8 90 x16 90 I ...
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PDF: 09005aef826aa906 1Gb_DDR3_SDRAM.pdf – Rev. J 05/10 EN Electrical Characteristics – I 6a. When T < 0°C: I and I C DD2P DD3P ed by 2%; and I and I must be derated by 7%. DD6 DD7 6b. When T ...
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Electrical Specifications – DC and AC DC Operating Conditions Table 21: DC Electrical Characteristics and Operating Conditions All voltages are referenced Parameter/Condition Supply voltage I/O supply voltage Input leakage current Any input 0V ≤ V ≤ V ...
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Table 23: Input Switching Conditions Parameter/Condition Input high AC voltage: Logic 1 @ 175mV Input high AC voltage: Logic 1 @ 150mV Input high AC voltage: Logic 1 @ 135 mV Input high AC voltage: Logic ...
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Figure 15: Input Signal Minimum V and V levels IH(AC) 0.925V V IH(DC) 0.850V 0.780V 0.765V 0.750V 0.735V 0.720V 0.650V V IL(DC) 0.575V V IL(AC) Note: 1. Numbers in diagrams reflect nominal values. PDF: 09005aef826aa906 1Gb_DDR3_SDRAM.pdf – ...
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AC Overshoot/Undershoot Specification Table 24: Control and Address Pins Parameter Maximum peak amplitude allowed for overshoot area (see Figure 16) Maximum peak amplitude allowed for undershoot area (see Figure 17) Maximum overshoot area above V Maximum undershoot area below V ...
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Table 26: Differential Input Operating Conditions (CK, CK# and DQS, DQS#) Parameter/Condition Differential input voltage logic high - slew Differential input voltage logic low - slew Differential input voltage logic high Differential input voltage logic low Differential input crossing voltage ...
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Figure 19: Single-Ended Requirements for Differential Signals Figure 20: Definition of Differential AC-Swing and V IH,diff(AC)min V IH,diff,min V IH,diff(DC)min V IL,diff(DC)max V IL,diff,max V IL,diff(AC)max Table 27: Allowed Time Before Ringback ...
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Table 27: Allowed Time Before Ringback ( DQS# (Continued) Note: 1. Below V Slew Rate Definitions for Single-Ended Input Signals Setup ( tween the last crossing of V nominal slew rate for a falling signal is defined as the slew ...
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Figure 21: Nominal Slew Rate Definition for Single-Ended Input Signals Setup Hold PDF: 09005aef826aa906 1Gb_DDR3_SDRAM.pdf – Rev. J 05/10 EN Electrical Specifications – DC and AC ΔTFS ΔTFH 53 Micron Technology, Inc. reserves the right to change products or specifications ...
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Slew Rate Definitions for Differential Input Signals Input slew rate for differential signals (CK, CK# and DQS, DQS#) are defined and meas- ured, as shown in Table 29 and Figure 22. The nominal slew rate for a rising signal is ...
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ODT Characteristics ODT effective resistance R DM, DQS, DQS#, and TDQS, TDQS# balls (x8 devices only). The ODT target values and a functional representation are listed in Table 30 and Table 31 (page 56). The individu- al pull-up and pull-down ...
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R TT • • Table 31: R Effective Impedances TT MR1 [ Resistor TT 120Ω TT120(PD240) R TT120(PU240) 120Ω 60Ω TT60(PD120) R TT60(PU120) 60Ω ...
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Table 31: R Effective Impedances (Continued) TT MR1 [ Resistor TT 20Ω TT20(PD40) R TT20(PU40) 20Ω 1. Values assume an RZQ of 240Ω (±1%). Note: ODT Sensitivity If either the temperature or voltage ...
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Figure 24: ODT Timing Reference Load CK, CK# Table 34: ODT Timing Definitions Symbol Begin Point Definition t AON Rising edge CK# defined by the end point of ODTL on t AOF Rising edge ...
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Figure 25: AON and AOF Definitions t AON Begin point: Rising edge CK# defined by the end point of ODTL on CK CK# DQ, DM DQS, DQS# TDQS, TDQS# V SSQ t t Figure 26: ...
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Figure 27: ADC Definition Begin point: Rising edge CK# defined by the end point of ODTL CK CK# V RTT,nom DQ, DM End point: DQS, DQS# Extrapolated TDQS, TDQS# point at V PDF: 09005aef826aa906 1Gb_DDR3_SDRAM.pdf – ...
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Output Driver Impedance The output driver impedance is selected by MR1[5,1] during initialization. The selected value is able to maintain the tight tolerances specified if proper ZQ calibration is per- formed. Output specifications refer to the default output driver unless ...
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Ohm Output Driver Impedance The 34Ω driver (MR1[ 01) is the default driver. Unless otherwise stated, all timings and specifications listed herein apply to the 34Ω driver only. Its impedance R fined by the value of the ...
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Ohm Driver The 34Ω driver’s current range has been calculated and summarized in Table 38 (page 63 1.42V. The individual pull-up and pull-down resistors (R DD are defined as follows: • R ON34(PD) • R ON34(PU) ...
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Table 40: 34 Ohm Driver I OH MR1[5,1] R Resistor ON 34.3Ω ON34(PD) R ON34(PU) 34 Ohm Output Driver Sensitivity If either the temperature or the voltage changes after ZQ calibration, then the tolerance limits listed in ...
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Alternative 40 Ohm Driver Table 43: 40 Ohm Driver Impedance Characteristics MR1[5,1] R Resistor ON 40Ω 0 Pull-up/pull-down mismatch (MM 1. Tolerance limits assume RZQ of 240Ω (±1%) and are applicable after proper ZQ calibra- Notes: 2. Measurement ...
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Table 45: 40 Ohm Output Driver Voltage and Temperature Sensitivity PDF: 09005aef826aa906 1Gb_DDR3_SDRAM.pdf – Rev. J 05/10 EN Change Min dR dTM dVM dTL dVL dTH 0 ON ...
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Output Characteristics and Operating Conditions The DRAM uses both single-ended and differential output drivers. The single-ended out- put driver is summarized below, while the differential output driver is summarized in Table 46 while the differential output driver is summarized in ...
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Table 47: Differential Output Driver Characteristics All voltages are referenced Parameter/Condition Output leakage current: DQ are disabled; 0V ≤ ODT is disabled; ODT is HIGH DDQ Output slew rate: Differential; For rising and falling ...
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Figure 30: Differential Output Signal X Reference Output Load Figure 31 represents the effective reference load of 25Ω used in defining the relevant device AC timing parameters (except ODT reference timing) as well as the output slew rate measurements. It ...
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Slew Rate Definitions for Single-Ended Output Signals The single-ended output driver is summarized in Table 46 (page 67). With the reference load for timing measurements, the output slew rate for falling and rising edges is de- fined and measured between ...
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Slew Rate Definitions for Differential Output Signals The differential output driver is summarized in Table 47 (page 68). With the reference load for timing measurements, the output slew rate for falling and rising edges is de- fined and measured between ...
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Speed Bin Tables Table 50: DDR3-1066 Speed Bins DDR3-1066 Speed Bin t t CL- RCD- RP Parameter ACTIVATE to internal READ or WRITE delay time PRECHARGE command period ACTIVATE-to-ACTIVATE or REFRESH command period ACTIVATE-to-PRECHARGE command period CWL ...
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Table 51: DDR3-1333 Speed Bins DDR3-1333 Speed Bin t t CL- RCD- RP Parameter ACTIVATE to internal READ or WRITE delay time PRECHARGE command period ACTIVATE-to-ACTIVATE or REFRESH command period ACTIVATE-to-PRECHARGE command period CWL = 5 CWL ...
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Table 52: DDR3-1600 Speed Bins DDR3-1600 Speed Bin t t CL- RCD- RP Parameter ACTIVATE to internal READ or WRITE delay time PRECHARGE command period ACTIVATE-to-ACTIVATE or REFRESH command period ACTIVATE-to-PRECHARGE command period CWL = 5 CWL ...
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Table 53: DDR3-1866 Speed Bins DDR3-1866 Speed Bin t t CL- RCD- RP Parameter Internal READ command to first data ACTIVATE to internal READ or WRITE delay time PRECHARGE command period ACTIVATE-to-ACTIVATE or REFRESH command period ACTIVATE-to-PRECHARGE command period CL ...
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Electrical Characteristics and AC Operating Conditions Table 54: Electrical Characteristics and AC Operating Conditions Notes 1–8 apply to the entire table Parameter Clock period average 0°C to 85°C C DLL disable mode T = >85°C to 95°C C ...
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Table 54: Electrical Characteristics and AC Operating Conditions (Continued) Notes 1–8 apply to the entire table Parameter Data setup time to Base (specification) DQS, DQS V/ns REF Data setup time to Base (specification) DQS, DQS ...
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Table 54: Electrical Characteristics and AC Operating Conditions (Continued) Notes 1–8 apply to the entire table Parameter DQS, DQS# High-Z time (RL + BL/2) DQS, DQS# differential READ preamble DQS, DQS# differential READ postamble DLL locking time CTRL, CMD, ADDR ...
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Table 54: Electrical Characteristics and AC Operating Conditions (Continued) Notes 1–8 apply to the entire table Parameter MULTIPURPOSE REGISTER READ burst end to mode register set for multipurpose register exit ZQCL command: Long POWER-UP and RE- calibration time SET operation ...
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Table 54: Electrical Characteristics and AC Operating Conditions (Continued) Notes 1–8 apply to the entire table Parameter Valid clocks before self refresh exit, power-down exit, or reset exit CKE MIN pulse width Command pass disable delay Power-down entry to power-down ...
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Table 54: Electrical Characteristics and AC Operating Conditions (Continued) Notes 1–8 apply to the entire table Parameter R synchronous turn-on delay TT R synchronous turn-off delay TT R turn-on from ODTL on reference TT R turn-off from ODTL off reference ...
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Parameters are applicable with 0°C ≤ T Notes: 2. All voltages are referenced Output timings are only valid for R 4. The unit 5. AC timing and I 6. All timings that use time-based values (ns, ...
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The setup and hold times are listed converting the base specification values (to which 21. When the device is operated with input clock jitter, this parameter needs to be derated 22. Single-ended signal parameter. 23. The DRAM output timing ...
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Although CKE is allowed to be registered LOW after a REFRESH command when 38. ODT turn-on time MIN is when the device leaves High-Z and ODT resistance begins to 39. Half-clock output parameters must be derated by the actual ...
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Electrical Characteristics and AC Operating Conditions Table 55: Electrical Characteristics and AC Operating Conditions for Speed Extensions Notes 1–8 apply to the entire table Parameter Clock period average: DLL disable mode T = 0°C to 85° >85°C ...
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Table 55: Electrical Characteristics and AC Operating Conditions for Speed Extensions (Continued) Notes 1–8 apply to the entire table Parameter Cumulative error across 2 cycles 3 cycles 4 cycles 5 cycles 6 cycles 7 cycles 8 cycles 9 cycles 10 ...
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Table 55: Electrical Characteristics and AC Operating Conditions for Speed Extensions (Continued) Notes 1–8 apply to the entire table Parameter DQS, DQS# rising to CK, CK# rising DQS, DQS# differential input low pulse width DQS, DQS# differential input high pulse ...
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Table 55: Electrical Characteristics and AC Operating Conditions for Speed Extensions (Continued) Notes 1–8 apply to the entire table Parameter ACTIVATE-to-PRECHARGE command period ACTIVATE-to-ACTIVATE command period ACTIVATE-to-ACTIVATE minimum com- 1KB page size mand 2KB page size period Four ACTIVATE 1KB ...
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Table 55: Electrical Characteristics and AC Operating Conditions for Speed Extensions (Continued) Notes 1–8 apply to the entire table Parameter Begin power supply ramp to power supplies stable RESET# LOW to power supplies stable RESET# LOW to I/O and R ...
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Table 55: Electrical Characteristics and AC Operating Conditions for Speed Extensions (Continued) Notes 1–8 apply to the entire table Parameter Power-down entry period: ODT either synchronous or asynchronous Power-down exit period: ODT either synchronous or asynchronous ACTIVATE command to power-down ...
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Table 55: Electrical Characteristics and AC Operating Conditions for Speed Extensions (Continued) Notes 1–8 apply to the entire table Parameter Asynchronous R turn-off delay TT (power-down with DLL off) ODT HIGH time with WRITE command and BL8 ODT HIGH time ...
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Parameters are applicable with 0°C ≤ T Notes: 2. All voltages are referenced Output timings are only valid for R 4. The unit 5. AC timing and I 6. All timings that use time-based values (ns, ...
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The setup and hold times are listed converting the base specification values (to which 21. When the device is operated with input clock jitter, this parameter needs to be derated 22. Single-ended signal parameter. 23. The DRAM output timing ...
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Although CKE is allowed to be registered LOW after a REFRESH command when 38. ODT turn-on time MIN is when the device leaves High-Z and ODT resistance begins to 39. Half-clock output parameters must be derated by the actual ...
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Command and Address Setup, Hold, and Derating The total sheet (page 76)) to the Δ (page 96)), respectively. Example: transition, the input signal has to remain above/below V t VAC (see Table 58 (page 96)). Although the total setup time ...
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Table 57: Derating Values for AC175 Threshold: V CMD/ ADDR 4.0 V/ns 3.0 V/ns Slew Rate Δ Δ Δ 0.9 –2 ...
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Table 59: Derating Values for AC135 Threshold: V CMD/ ADDR 4.0 V/ns 3.0 V/ns Slew Rate Δ Δ Δ 0.9 2 ...
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Table 61: Minimum Required Time Below V IL(AC) t Slew Rate (V/ns) VAC at 175mV (ps) >2.0 75 2.0 57 1.5 50 1.0 38 0.9 34 0.8 29 0.7 22 0.6 13 0.5 <0.5 PDF: 09005aef826aa906 1Gb_DDR3_SDRAM.pdf – Rev. J ...
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Figure 34: Nominal Slew Rate and CK CK# DQS# DQS V DDQ V IH(AC)min V V IH(DC)min V REF(DC) V IL(DC)max V IL(DC)max V SS Setup slew rate falling signal 1. Both the clock and the strobe are drawn on ...
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Figure 35: Nominal Slew Rate for CK CK# DQS# DQS V DDQ V IH(AC)min V IH(DC)min REF(DC) V IL(DC)max V IL(AC)max V SS Hold slew rate rising signal 1. Both the clock and the strobe are ...
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Figure 36: Tangent Line for CK CK# DQS# DQS V DDQ V IH(AC)min V REF region V IH(DC)min V REF(DC) V IL(DC)max V IL(DC)max Nominal line Both the clock and the strobe are drawn on different time ...
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Figure 37: Tangent Line for CK CK# DQS# DQS V DDQ V IH(AC)min V IH(DC)min region V REF(DC region V IL( DC)max V IL( AC)max Both the clock and the strobe ...
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Data Setup, Hold, and Derating The total sheet ble 54 (page 76)) to the Δ respectively. Example: the input signal has to remain above/below V ble 66 (page 105)). Although the total setup time for slow slew rates might be ...
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Table 63: Derating Values for Shaded cells indicate slew rate combinations not supported 4.0 V/ns 3.0 V/ns DQ Slew Δ Δ Δ Δ Rate V/ 1.0 ...
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Table 65: Derating Values for Shaded cells indicate slew rate combinations not supported 4.0 V/ns 3.0 V/ns DQ Slew Δ Δ Δ Δ Rate V/ 1.0 ...
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Figure 38: Nominal Slew Rate and CK CK# DQS# DQS V DDQ V IH(AC)MIN V REF region V IH(DC)min V REF(DC) V IL(DC)max V IL(AC)max V SS Setup slew rate falling signal 1. Both the clock and the strobe are ...
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Figure 39: Nominal Slew Rate for CK CK# DQS# DQS V DDQ V IH(AC)min V IH(DC)min region V REF(DC) V IL(DC)max V IL(AC)max V SS Hold slew rate rising signal 1. Both the clock and the strobe ...
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Figure 40: Tangent Line for CK CK# DQS# DQS V DDQ V IH(AC)min V REF region V IH(DC)min V REF(DC) V IL(DC)max V IL(AC)max Nominal line Both the clock and the strobe are drawn on different time ...
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Figure 41: Tangent Line for CK CK# DQS# DQS V DDQ V IH(AC)min V IH(DC)min region V REF(DC region V IL(DC)max V IL(AC)max Both the clock and the strobe are drawn ...
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Commands – Truth Tables Table 67: Truth Table – Command Notes 1–5 apply to the entire table Function Symbol MODE REGISTER SET MRS REFRESH REF Self refresh entry SRE Self refresh exit SRX Single-bank PRECHARGE PRE PRECHARGE all banks PREA ...
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RESET# is LOW enabled and used only for asynchronous reset. Thus, RESET# must be 3. The state of ODT does not affect the states described in this table. 4. Operations apply to the bank defined by the bank address. ...
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Table 68: Truth Table – CKE Notes 1–2 apply to the entire table; see Table 67 (page 110) for additional command details Previous Cycle 3 Current State ( Power-down L L Self refresh L L Bank(s) active H ...
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Commands DESELECT The DESELT (DES) command (CS# HIGH) prevents new commands from being execu- ted by the DRAM. Operations already in progress are not affected. NO OPERATION The NO OPERATION (NOP) command (CS# LOW) prevents unwanted commands from being registered ...
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... The value on input A12 (if enabled in the MR) when the WRITE command is issued determines whether BC4 (chop) or BL8 is used. Input data appearing on the DQ is written to the memory array subject to the DM input logic level appearing coincident with the data given DM signal is registered LOW, the corresponding data will be written to memory ...
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A READ or WRITE command to a different bank is allowed during concurrent auto precharge as long as it does not interrupt the data transfer in the current bank and does not violate any other timing parameters. Input A10 ...
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Figure 42: Refresh Mode T0 T1 CK# CK CKE NOP 1 Command PRE Address All banks A10 One bank Bank(s) 3 BA[2:0] DQS, DQS NOP commands are shown for ease of illustration; other valid ...
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DLL Disable Mode If the DLL is disabled by the mode register (MR1[0] can be switched during initialization or later), the DRAM is targeted, but not guaranteed, to operate similarly to the normal mode with a few notable exceptions: • ...
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Figure 43: DLL Enable Mode to DLL Disable Mode T0 T1 CK# CK CKE MRS 2 Command NOP t MOD 6 ODT 9 Notes: 1. Any valid command. 2. Disable DLL by setting MR1[ Enter SELF REFRESH. ...
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Figure 44: DLL Disable Mode to DLL Enable Mode T0 Ta0 CK# CK CKE SRE 1 Command NOP t CKSRE 7 ODTL off + 1 × ODT 10 Notes: 1. Enter SELF REFRESH. 2. Exit SELF REFRESH. 3. ...
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Figure 45: DLL Disable DQSCK Timing T0 T1 CK# CK READ NOP Command Valid Address DQS, DQS# DLL on DQ BL8 DLL on RL (DLL disable ( DQS, DQS# DLL off DQ ...
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Input Clock Frequency Change When the DDR3 SDRAM is initialized, it requires the clock to be stable during most nor- mal states of operation. This means that after the clock frequency has been set to the stable state, the clock ...
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Figure 46: Change Frequency During Precharge Power-Down Previous clock frequency CKSRE CKE t CPDED Command NOP NOP Address t AOFPD/ t AOF ODT DQS, DQS# ...
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... For better signal integrity, DDR3 SDRAM memory modules adopted fly-by topology for the commands, addresses, control signals, and clocks. Write leveling is a scheme for the memory controller to adjust or deskew the DQS strobe (DQS, DQS relationship at the DRAM with a simple feedback feature provided by the DRAM. Write leveling is generally used as part of the initialization process, if required ...
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When write leveling is enabled, the rising edge of DQS samples CK, and the prime DQ outputs the sampled CK’s status. The prime DQ for configuration is DQ0 with all other DQ (DQ[7:1]) driving LOW. The ...
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... NOP or DES commands are allowed. The memory controller should attempt to level only one rank at a time; thus, the outputs of other ranks should be disabled by setting MR1[12 the other ranks. The memory con- troller may assert ODT after a ODT transition ...
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Figure 48: Write Leveling Sequence CK# CK MRS 1 NOP 2 Command t MOD ODT t WLDQSEN Differential DQS 4 Prime DQ 5 Early remaining DQ Late remaining DQ 1. MRS: Load MR1 to enter write leveling mode. Notes: 2. ...
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... After the last rising DQS (capturing T0), the memory controller should stop driving the DQS signals after ble the memory controller to capture the applicable prime DQ state (at ~Tb0). The DQ balls become undefined when DQS no longer remains LOW, and they remain unde- ...
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Initialization The following sequence is required for power up and initialization, as shown in Fig- ure 50 (page 129): 1. Apply power. RESET# is recommended to be below 0.2 × Until stable power, maintain RESET# LOW to ensure ...
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Figure 50: Initialization Sequence T (MAX) = 200ms V See power-up DD conditions in the V DDQ initialization sequence text, V set REF Power-up ramp CK 20ns RESET# T (MIN) = ...
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... MRS command is issued. Reprogramming the mode register will not alter the contents of the memory array, provided it is performed correctly. The MRS command can only be issued (or reissued) when all banks are idle and in the ...
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Figure 52: MRS to nonMRS Command Timing ( Command Address CKE 1. Prior to issuing the MRS command, all banks must be idle (they must be precharged, Notes: 2. Prior to Ta2 when CKE must be ...
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The programmed burst length applies to both READ and WRITE bursts. Figure 53: Mode Register 0 (MR0) Definitions M15 M14 Mode Register 0 0 Mode register 0 (MR0 Mode register 1 (MR1) 1 ...
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Table 73: Burst Order Starting Burst READ/ Column Address Length WRITE (A[2, 1, 0]) 4 chop READ ...
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Precharge Power-Down (Precharge PD) The precharge PD bit applies only when precharge power-down mode is being used. When MR0[12] is set to 0, the DLL is off during precharge power-down providing a low- er standby current ...
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... MRS command and retains the stored information until it is reprogrammed, until RE- SET# goes LOW, or until the device loses power. Reprogramming the MR1 register will not alter the contents of the memory array, provided it is performed correctly. The MR1 register must be loaded when all banks are idle and no bursts are in progress. ...
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If the DLL is enabled prior to entering self refresh mode, the DLL is automatically disa- bled when entering SELF REFRESH operation and is automatically reenabled and reset upon exit of SELF REFRESH operation. If the DLL is disabled prior ...
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... The actual effective termination, R nonlinearity of the termination. For R nation (ODT) (page 187)). The ODT feature is designed to improve signal integrity of the memory channel by ena- bling the DDR3 SDRAM controller to independently turn on/off ODT for any or all devices. The ODT input control pin is used to determine when R on) and off (ODTL off), assuming ODT has been enabled via MR1[ ...
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... MRS command and will retain the stored information until it is programmed again or until the device loses power. Reprogramming the MR2 register will not alter the contents of the memory array, provided it is performed correctly. The MR2 register must be loaded when all banks are idle and no data bursts are in progress, and the controller must wait the specified time sequent operation ...
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Figure 57: Mode Register 2 (MR2) Definition M15 M14 MR2[16, 13:11, 8, and 2:0] are reserved for future use and must all be programmed to 0. Note: CAS Write Latency (CWL) CWL is defined by ...
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In the disabled mode, ASR requires the user to ensure the DRAM never exceeds a T bles the SRT feature listed below when the T Enabling ASR assumes the DRAM self refresh rate ...
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... LOAD MODE command and retains the stored information until it is programmed again or until the device loses power. Reprogramming the MR3 register will not alter the contents of the memory array, provided it is performed correctly. The MR3 register must be loaded when all banks are idle and no data bursts are in progress, and the controller must wait the specified time sequent operation ...
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... Figure 60: Multipurpose Register (MPR) Block Diagram Memory core 1. A predefined data pattern can be read out of the MPR with an external READ command. Notes: 2. MR3[2] defines whether the data flow comes from the memory core or the MPR. When Table 74: MPR Functional Description of MR3 Bits MR3[2] MR3[1:0] ...
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DQs driven LOW, or for all DQs to output the MPR data. The MPR readout supports fixed READ burst and READ burst chop (MRS and OTF via A12/BC#) with regular READ latencies and AC timings applicable, provided the DLL is ...
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Table 75: MPR Readouts and Burst Order Bit Mapping (Continued) MR3[2] MR3[1:0] Function 1 11 Note: 1. Burst order bit 0 is assigned to LSB, and burst order bit 7 is assigned to MSB of the selec- PDF: 09005aef826aa906 1Gb_DDR3_SDRAM.pdf ...
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... Valid A10/ Valid A11 0 Valid Valid 1 A12/BC# 0 A[15:13] 0 Valid DQS, DQS READ with BL8 either by MRS or OTF. Notes: 2. Memory controller must drive 0 on A[2:0]. Tc0 Tc1 Tc2 Tc3 Tc4 NOP NOP NOP NOP NOP RL Tc5 Tc6 Tc7 Tc8 Tc9 NOP NOP ...
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... Valid A11 0 Valid Valid Valid 1 A12/BC# 0 Valid A[15:13] 0 Valid Valid RL DQS, DQS# DQ Notes: 1. READ with BL8 either by MRS or OTF. 2. Memory controller must drive 0 on A[2:0]. Tc1 Tc2 Tc3 Tc4 Tc5 NOP NOP NOP NOP NOP RL Tc6 Tc7 Tc8 Tc9 Tc10 NOP ...
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... Valid Valid 1 Valid 1 A12/BC# 0 A[15:13] 0 Valid Valid RL DQS, DQS READ with BC4 either by MRS or OTF. Notes: 2. Memory controller must drive 0 on A[1:0 selects lower 4 nibble bits selects upper 4 nibble bits Tc1 Tc2 Tc3 Tc4 Tc5 NOP NOP NOP NOP NOP RL Tc6 ...
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... Valid Valid 1 Valid 1 A12/BC# 0 A[15:13] 0 Valid Valid RL DQS, DQS READ with BC4 either by MRS or OTF. Notes: 2. Memory controller must drive 0 on A[1:0 selects upper 4 nibble bits selects lower 4 nibble bits Tc1 Tc2 Tc3 Tc4 Tc5 NOP NOP NOP NOP NOP RL Tc6 ...
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... MRD and MOD are satisfied from the last MRS, the regular DRAM com- mands (such as activate a memory bank for regular read or write access) are permitted satisfied and no data bursts are in progress). The controller t MRD before initiating a subsequent operation such MOD ...
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ZQ CALIBRATION Operation The ZQ CALIBRATION command is used to calibrate the DRAM output drivers (R and ODT values (R 240Ω (±1%) external resistor is connected from the DRAM’s ZQ ball to V DDR3 SDRAM need a longer time to ...
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ACTIVATE Operation Before any READ or WRITE commands can be issued to a bank within the DRAM, a row in that bank must be opened (activated). This is accomplished via the ACTIVATE com- mand, which selects both the bank and ...
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Figure 67: Example: FAW T0 T1 CK# CK Command ACT NOP Address Row BA[2:0] Bank a t RRD PDF: 09005aef826aa906 1Gb_DDR3_SDRAM.pdf – Rev. J 05/ ACT NOP ACT Row Row Bank b Bank c t ...
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READ Operation READ bursts are initiated with a READ command. The starting column and bank ad- dresses are provided with the READ command and auto precharge is either enabled or disabled for that burst access. If auto precharge is enabled, ...
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DDR3 SDRAM does not allow interrupting or truncating any READ burst. Data from any READ burst must be completed before a subsequent WRITE burst is al- lowed. An example of a READ burst followed by a ...
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Figure 69: Consecutive READ Bursts (BL8 CK# CK Command 1 READ NOP NOP NOP t CCD Bank, Address 2 Col n DQS, DQS NOP commands are shown for ease of ...
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Figure 71: Nonconsecutive READ Bursts CK# CK Command READ NOP NOP NOP NOP Bank a, Address Col DQS, DQS Notes ...
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Figure 73: READ (BC4) to WRITE (BC4) OTF CK# CK Command 1 READ NOP NOP NOP READ-to-WRITE command delay = CCD Bank, Address 2 Col n DQS, ...
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Figure 75: READ to PRECHARGE (BC4 CK# CK Command READ NOP NOP NOP NOP Bank a, Address Col n t RTP DQS, DQS RAS Figure 76: READ to PRECHARGE ( ...
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DQS to DQ output timing is shown in Figure 78 (page 160). The DQ transitions be- tween valid data outputs must be within DQS must also maintain a minimum HIGH and LOW time of the READ preamble, the DQ balls ...
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Figure 78: Data Output Timing – DQSQ and Data Valid Window T0 T1 CK# CK Command 1 READ NOP Bank, Address 2 Col n DQS, DQS (last data valid (first data no longer valid) All ...
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HZ and parameters are referenced to a specific voltage level which specifies when the device output is no longer driving (DQ). Figure 80 (page 162) shows a method to calculate the point when the device is no longer driving ...
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Figure 80: Method for Calculating t HZ (DQS (DQ (DQS (DQ) end point = 2 × Within a burst, the rising strobe edge is not necessarily fixed at Notes: 2. ...
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Figure 82: RPST Timing Single-ended signal, provided as background information DQS# Single-ended signal, provided as background information DQS - DQS# Resulting differential signal relevant for t RPST specification PDF: 09005aef826aa906 1Gb_DDR3_SDRAM.pdf – Rev. J 05/ CK# DQS ...
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WRITE Operation WRITE bursts are initiated with a WRITE command. The starting column and bank ad- dresses are provided with the WRITE command, and auto precharge is either enabled or disabled for that access. If auto precharge is selected, the ...
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Figure 83: WPRE Timing CK CK# DQS - DQS# Resulting differential signal relevant for t WPRE specification t Figure 84: WPST Timing CK CK# DQS - DQS# Resulting differential signal relevant for t WPST specification PDF: 09005aef826aa906 1Gb_DDR3_SDRAM.pdf – ...
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Figure 85: WRITE Burst CK# CK Command 1 WRITE NOP NOP CWL Bank, Address 2 Col n t DQSS (MIN) DQS, DQS DQSS (NOM) DQS, DQS DQSS ...
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Figure 86: Consecutive WRITE (BL8) to WRITE (BL8 CK# CK Command 1 WRITE NOP NOP NOP t CCD Address 2 Valid DQS, DQS NOP commands are shown for ease of ...
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Figure 88: Nonconsecutive WRITE to WRITE CK# CK Command WRITE NOP NOP NOP NOP Address Valid WL = CWL + DQS, DQS Notes ( data-in ...
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Figure 90: WRITE to READ (BC4 Mode Register Setting CK# CK Command 1 WRITE NOP NOP Address 3 Valid DQS, DQS NOP commands are shown for ease of illustration; other commands ...
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Figure 91: WRITE (BC4 OTF) to READ (BC4 OTF CK# CK Command 1 WRITE NOP NOP NOP Address 3 Valid DQS, DQS Notes: 1. NOP commands are shown for ease of ...
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Figure 92: WRITE (BL8) to PRECHARGE CK# CK Command WRITE NOP NOP NOP Valid Address CWL DQS, DQS# DQ BL8 data-in from column n. Notes: 2. Seven subsequent ...
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Figure 94: WRITE (BC4 OTF) to PRECHARGE CK# CK Command 1 WRITE NOP NOP Bank, Address 3 Col n DQS, DQS NOP commands are shown for ease of illustration; other commands may be valid ...
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Figure 95: Data Input Timing DQS, DQS# PDF: 09005aef826aa906 1Gb_DDR3_SDRAM.pdf – Rev. J 05/ WPRE t DQSH t DQSL 173 1Gb: x4, x8, x16 DDR3 SDRAM t DH Transitioning Data Micron Technology, ...
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PRECHARGE Operation Input A10 determines whether one bank or all banks are to be precharged, and in the case where only one bank precharged, inputs BA[2:0] select the bank. When all banks are to be precharged, inputs ...
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Figure 96: Self Refresh Entry/Exit Timing CKSRE CPDED CKE t IS ODT 2 RESET# 2 SRE (REF) 3 NOP 4 Command NOP Address Enter self refresh mode (synchronous) ...
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Extended Temperature Usage Micron’s DDR3 SDRAM supports the optional extended temperature range of 0°C to +95°C, T The extended temperature range DRAM must be refreshed externally at 2X (double re- fresh) anytime the case temperature is above +85°C (and does ...
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Power-Down Mode Power-down is synchronously entered when CKE is registered LOW coincident with a NOP or DES command. CKE is not allowed to go LOW while either an MRS, MPR, ZQCAL, READ, or WRITE operation is in progress. CKE is ...
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A summary of the two power-down modes is listed in Table 79 (page 178). While in either power-down state, CKE is held LOW, RESET# is held HIGH, and a stable clock signal must be maintained. ODT ...
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Figure 97: Active Power-Down Entry and Exit Command Valid NOP t IS CKE t IH Address Valid Enter power-down mode PDF: 09005aef826aa906 1Gb_DDR3_SDRAM.pdf – Rev. J 05/ Ta0 t CL ...
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Figure 98: Precharge Power-Down (Fast-Exit Mode) Entry and Exit Command NOP t IS CKE Enter power-down mode Figure 99: Precharge Power-Down (Slow-Exit Mode) Entry and Exit ...
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Figure 100: Power-Down Entry After READ or READ with Auto Precharge (RDAP Ta0 Ta1 CK# CK READ/ NOP NOP NOP Command RDAP CKE Address Valid DQS, DQS# DQ BL8 DQ BC4 Figure 101: ...
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Figure 102: Power-Down Entry After WRITE with Auto Precharge (WRAP Ta0 Ta1 CK# CK Command WRAP NOP NOP NOP CKE Address Valid A10 CWL DQS, DQS# DQ BL8 DQ BC4 1. Notes: 2. CKE ...
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Figure 104: ACTIVATE to Power-Down Entry Command ACTIVE Address Valid CKE t ACTPDEN Figure 105: PRECHARGE to Power-Down Entry Command PRE All/single Address bank ...
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Figure 106: MRS Command to Power-Down Entry Command MRS NOP Address Valid CKE Figure 107: Power-Down Exit to Refresh to Power-Down Entry Command NOP ...
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RESET Operation The RESET signal (RESET asynchronous signal that triggers any time it drops LOW, and there are no restrictions about when it can go LOW. After RESET# goes LOW, it must remain LOW for 100ns. During this ...
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Figure 108: RESET Sequence System RESET (warm boot) Stable and valid clock CK (MIN) = MAX (10ns CK 100ns (MIN) t IOZ = 20ns RESET 10ns (MIN) CKE ODT ...
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... TDQS, TDQS# for the x8 configuration, when enabled). ODT is applied to each DQ, UDQS, UDQS#, LDQS, LDQS#, UDM, and LDM signal for the x16 configuration. The ODT feature is designed to improve signal integrity of the memory channel by ena- bling the DRAM controller to independently turn on/off the DRAM’s internal termina- tion resistance for any grouping of DRAM devices ...
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Table 80: Truth Table – ODT (Nominal) Note 1 applies to the entire table MR1[ ODT Pin 000 0 000 1 000–101 0 000–101 1 110 and 111 X 1. Assumes dynamic ODT is disabled (see Dynamic ODT ...
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Dynamic ODT In certain application cases, and to further enhance signal integrity on the data bus desirable that the termination strength of the DDR3 SDRAM can be changed without issuing an MRS command, essentially changing the ODT termination ...
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Table 83: Mode Registers for R MR1 (R ) TT,nom RZQ = 240Ω Note: Table 84: Mode Registers ...
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Figure 110: Dynamic ODT: ODT Asserted Before and After the WRITE, BC4 CK# CK Command NOP NOP NOP NOP WRS4 NOP Address Valid ODTH4 ODT ODTL on t AON (MIN AON ...
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Figure 112: Dynamic ODT: ODT Pin Asserted Together with WRITE Command for 6 Clock Cycles, BL8 CK# CK NOP WRS8 NOP Command ODTL cnw Address Valid ODTL on ODT R TT DQS, DQS Via MRS ...
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Figure 113: Dynamic ODT: ODT Pin Asserted with WRITE Command for 6 Clock Cycles, BC4 CK# CK Command NOP WRS4 NOP ODTL Address Valid ODT R TT DQS, DQS Via MRS or OTF ...
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Synchronous ODT Mode Synchronous ODT mode is selected whenever the DLL is turned on and locked and when either R modes are: • Any bank active with CKE HIGH • Refresh mode with CKE HIGH • Idle mode with CKE ...
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Table 86: Synchronous ODT Parameters Symbol Description ODTL on ODT synchronous turn-on delay ODTL off ODT synchronous turn-off delay ODTH4 ODT minimum HIGH time after ODT assertion or WRITE (BC4) ODTH8 ODT minimum HIGH time after WRITE (BL8) t AON ...
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Figure 116: Synchronous ODT (BC4 CK# CK CKE Command NOP NOP NOP NOP NOP ODTH4 ODT ODTL Notes: TT,nom 2. ODT must be ...
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ODT Off During READs Because the device cannot terminate and drive at the same time least one-half clock cycle before the READ preamble by driving the ODT ball LOW (if either R amble, as shown in the following ...
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Figure 117: ODT During READs CK# CK Command READ NOP NOP NOP NOP Address Valid ODTL off = CWL + ODT DQS, DQS# DQ Note: 1. ODT must be ...
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Asynchronous ODT Mode Asynchronous ODT mode is available when the DRAM runs in DLL on mode and when either R charged power-down standby (via MR0[12]). Additionally, ODT operates asynchronous- ly when the DLL is synchronizing after being reset. See Power-Down ...
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Figure 118: Asynchronous ODT Timing with Fast ODT Transition CK# CK CKE ODT t AONPD (MIN Note ignored. Table 87: Asynchronous ODT Timing Parameters for All ...