MT41J64M16LA-187E:B TR Micron Technology Inc, MT41J64M16LA-187E:B TR Datasheet - Page 175

• Manufacturer Part Number: MT41J64M16LA-187E:B TR
• Description: IC DDR3 SDRAM 1GBIT 96FBGA
• Manufacturer: Micron Technology Inc
• Type: DDR3 SDRAMr

Specifications of MT41J64M16LA-187E:B TR

• Format - Memory: RAM
• Memory Type: DDR3 SDRAM
• Memory Size: 1G (64M x 16)
• Speed: 533MHz
• Interface: Parallel
• Voltage - Supply: 1.425 V ~ 1.575 V
• Operating Temperature: 0°C ~ 95°C
• Package / Case: 96-FBGA
• Organization: 64Mx16
• Density: 1Gb
• Address Bus: 16b
• Maximum Clock Rate: 1.066GHz
• Operating Supply Voltage (typ): 1.5V
• Package Type: FBGA
• Operating Temp Range: 0C to 95C
• Operating Supply Voltage (max): 1.575V
• Operating Supply Voltage (min): 1.425V
• Supply Current: 265mA
• Pin Count: 96
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 557-1378-2

Figure 96: Self Refresh Entry/Exit Timing
Command
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf – Rev. J 05/10 EN
RESET# 2
Address
ODT 2
CK#
CKE
CK
T0
NOP
t RP 8
Enter self refresh mode
(synchronous)
SRE (REF) 3
t IS
t IS
Notes:
T1
t CPDED
1. The clock must be valid and stable meeting
2. ODT must be disabled and R
3. Self refresh entry (SRE) is synchronous via a REFRESH command with CKE LOW.
4. A NOP or DES command is required at T2 after the SRE command is issued prior to the
5. NOP or DES commands are required prior to exiting self refresh mode until state Te0.
6.
7.
8. The device must be in the all banks idle state prior to entering self refresh mode. For
9. Self refresh exit is asynchronous; however,
t CKSRE 1
NOP 4
T2
ing self refresh mode, and at least
is stopped or altered between states Ta0 and Tb0. If the clock remains valid and un-
changed from entry and during self refresh mode, then
apply; however,
R
inputs becoming “Don’t Care.”
t
t
example, all banks must be precharged,
progress.
clock edge where CKE HIGH satisfies
t
XS is required before any commands not requiring a locked DLL.
XSDLL is required before any commands requiring a locked DLL.
ISXR is satisfied at Tc1.
TT,nom
and R
Ta0
TT(WR)
t CKESR (MIN) 1
t
CKESR must be satisfied prior to exiting at SRX.
are disabled in the mode registers, ODT can be a “Don’t Care.”
175
Tb0
TT
off prior to entering self refresh at state T1. If both
t
CKSRX prior to exiting self refresh mode, if the clock
t CKSRX 1
Micron Technology, Inc. reserves the right to change products or specifications without notice.
t
ISXR at Tc1.
Tc0
t IH
t
RP must be met, and no data bursts can be in
t
XS and
Exit self refresh mode
t
1Gb: x4, x8, x16 DDR3 SDRAM
CK specifications at least
SRX (NOP)
(asynchronous)
t IS
Tc1
t
CKSRX timing is also measured so that
t
XSDLL timings start at the first rising
SELF REFRESH Operation
t
CKSRE and
NOP 5
Td0
© 2006 Micron Technology, Inc. All rights reserved.
Indicates A Break in
Time Scale
t
CKSRX do not
t
CKSRE after enter-
Valid 6
Valid
Valid
Te0
Valid 7
Don’t Care
Valid
Valid
Valid
Tf0