MT41J64M16LA-187E:B TR Micron Technology Inc, MT41J64M16LA-187E:B TR Datasheet - Page 127

• Manufacturer Part Number: MT41J64M16LA-187E:B TR
• Description: IC DDR3 SDRAM 1GBIT 96FBGA
• Manufacturer: Micron Technology Inc
• Type: DDR3 SDRAMr

Specifications of MT41J64M16LA-187E:B TR

• Format - Memory: RAM
• Memory Type: DDR3 SDRAM
• Memory Size: 1G (64M x 16)
• Speed: 533MHz
• Interface: Parallel
• Voltage - Supply: 1.425 V ~ 1.575 V
• Operating Temperature: 0°C ~ 95°C
• Package / Case: 96-FBGA
• Organization: 64Mx16
• Density: 1Gb
• Address Bus: 16b
• Maximum Clock Rate: 1.066GHz
• Operating Supply Voltage (typ): 1.5V
• Package Type: FBGA
• Operating Temp Range: 0C to 95C
• Operating Supply Voltage (max): 1.575V
• Operating Supply Voltage (min): 1.425V
• Supply Current: 265mA
• Pin Count: 96
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 557-1378-2

Write Leveling Mode Exit Procedure
Figure 49: Exit Write Leveling
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf – Rev. J 05/10 EN
R
TT
DQS, R
DQS, DQS#
Command
TT
Address
R
DQS#
TT(DQ)
ODT
CK#
CK
DQ
NOP
T0
Note:
NOP
T1
t WLO + t WLOE
After the DRAM are leveled, they must exit from write leveling mode before the normal
mode can be used. Figure 49 (page 127) depicts a general procedure in exiting write
leveling mode. After the last rising DQS (capturing a 1 at T0), the memory controller
should stop driving the DQS signals after
ble the memory controller to capture the applicable prime DQ state (at ~Tb0). The DQ
balls become undefined when DQS no longer remains LOW, and they remain unde-
fined until
The ODT input should be deasserted LOW such that ODTL off (MIN) expires after the
DQS is no longer driving LOW. When ODT LOW satisfies
~Tb0) until the DRAM is ready for either another rank to be leveled or until the normal
mode can be used. After DQS termination is switched off, write level mode should be
disabled via the MRS command (at Tc2). After
mand may be registered by the DRAM. Some MRS commands may be issued after
t
MRD (at Td1).
1. The DQ result, = 1, between Ta0 and Tc0, is a result of the DQS, DQS# signals capturing
CK HIGH just after the T0 state.
R
TT,nom
NOP
T2
t
MOD after the MRS command (at Te1).
Ta0
NOP
Indicates a break in
time scale
CK = 1
NOP
Tb0
ODTL off
127
NOP
Tc0
t AOF (MAX)
t AOF (MIN)
NOP
Tc1
Micron Technology, Inc. reserves the right to change products or specifications without notice.
Undefined Driving Mode
t
WLO (MAX) delay plus enough delay to ena-
t
MRS
MR1
1Gb: x4, x8, x16 DDR3 SDRAM
MOD is satisfied (at Te1), any valid com-
Tc2
t MRD
NOP
Td0
t
IS, ODT must be kept LOW (at
t MOD
© 2006 Micron Technology, Inc. All rights reserved.
Valid
Valid
Td1
Transitioning
Write Leveling
NOP
Te0
Valid
Don’t Care
Valid
Te1