IDT70824L35PF IDT, Integrated Device Technology Inc, IDT70824L35PF Datasheet - Page 16

• Manufacturer Part Number: IDT70824L35PF
• Description: IC SARAM 64KBIT 35NS 80TQFP
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT70824L35PF

• Format - Memory: RAM
• Memory Type: SARAM
• Memory Size: 64K (4K x 16)
• Speed: 35ns
• Interface: Parallel
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 80-TQFP, 80-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 70824L35PF

Sequential Port: Write, Pointer Load, Burst Read
Read STRT/EOB Flag Timing - Sequential Port
NOTES: (Also used in Figure "Read STRT/EOB Flag Timing")
1. If SSTRT
2. If CNTEN = V
3. SOE will control the output and should be HIGH on power-up. If SCE = V
4. Unlike SLD case, CNTEN is not disabled on cycle immediately following SSTRT.
5. If SR/W = V
6. SOE = V
NOTES:
1. If SLD = V
2. If CNTEN = V
3. Pointer is not incremented on cycle immediately following SLD even if CNTEN is LOW.
IDT70824S/L
High-Speed 4K x 16 Sequential Access Random Access Memory
cycle. If SCE = V
contention and permit a write on this cycle.
SI/O
SSTRT
CNTEN
SI/O
CNTEN
SCLK
SI/O
SR/W
EOB
SOE
SCE
SI/O
SLD
SCLK
SR/W
OUT
SOE
SCE
IL
1
OUT
IN
or SSTRT
1/2
1/2
IL
makes no difference at this point since the SR/W = V
IN
IL
, then address will be clocked in on the SCLK's rising edge.
, data would be written to D
IH
IH
for the SCLK's rising edge, the internal address counter will not advance.
for the SCLK's rising edge, the internal address counter will not advance.
IL
t
t
and is clocked in while SR/W = V
Dx
WS
WS
2
t
t
WS
WS
Dx
= V
t
t
WH
WH
t
IL
t
WH
WH
, then address will be clocked in on the SCLK's rising edge.
t
CH
t
CH
t
CYC
t
CYC
t
ES
t
ES
t
CL
t
t
CL
DS
A0
t
0
OLZ
(3)
again since CNTEN = V
t
SOE
(5)
t
t
IL
EH
DH
t
t
CD
, the data addressed will be written to if the last cycle was a read. SOE may be used to control the bus
EH
(1)
(1)
t
CKLZ
t
t
t
t
WS
WS
WS
WS
IL
D0
disables the output until SR/W = V
IH
t
(3)
t
t
t
(4)
WH
WH
.
WH
WH
HIGH IMPEDANCE
HIGH IMPEDANCE
t
IL
SOP
t
SD
and is clocked in while SR/W = V
t
16
t
OLZ
CKLZ
t
ES
t
ES
D1
D0
t
EH
t
EH
t
IH
Military and Commercial Temperature Ranges
EB
is clocked in on the next rising clock edge.
IH
D2
D1
, the data addressed will be read out within that
t
OHZ
t
OHZ
t
DS
(2)
t
D3
DS
(2)
D2
t
(2)
DH
(2)
t
DH
3099 drw19
3099 drw 18