IDT70824L35PF IDT, Integrated Device Technology Inc, IDT70824L35PF Datasheet - Page 9

• Manufacturer Part Number: IDT70824L35PF
• Description: IC SARAM 64KBIT 35NS 80TQFP
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT70824L35PF

• Format - Memory: RAM
• Memory Type: SARAM
• Memory Size: 64K (4K x 16)
• Speed: 35ns
• Interface: Parallel
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 80-TQFP, 80-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 70824L35PF

Reset (RST)
asynchronously of SCLK (i.e. not registered). The default states after a
reset operation are displayed in the adjacent chart.
Buffer Command Mode (CMD)
control the state of the two buffers. Address pins A
I/O
and to set the flow control mode of each buffer. The Buffer Command Mode
Random Access Port CMD Mode
NOTE:
1. R/W input "0(1)" indicates a write(0) or read(1) occurring with the same address input.
Cases 1 through 4: Start and End of Buffer Register Description
NOTES:
1. "H" = V
2. A write into the buffer occurs when R/W = V
Case 5: Buffer Flow Modes
for each buffer. Each buffer flow mode defines a unique set of actions for
the sequential port address pointer and EOB flags. In BUFFER CHAIN-
ING mode, after the address pointer reaches the end of the buffer, it sets
MSB
IDT70824S/L
High-Speed 4K x 16 Sequential Access Random Access Memory
11
Setting RST LOW resets the control state of the SARAM. RST functions
Buffer Command Mode (CMD) allows the random access port to
CE = V
Within the SARAM, the user can designate one of two buffer flow modes
Case #
are used to access the start of buffer and the end of buffer addresses
2
3
4
5
6
7
8
1
15
H
OH
IH
.
for I/O in the output state and "Don't Cares" for I/O in the input state. "L" = V
14
H
110/111
A
000
010
001
011
100
101
101
2
-A
0
13
H
12
L
R/W
0 (1)
0 (1)
0 (1)
0 (1)
0 (1)
(X)
0
1
11 --------------------------------------------------------------------------------------------------
Read only - flag status register.
(Reserved)
IL
Write (read) the start address of Buffer #1 through I/O
Write (read) the end address of Buffer #1 through I/O
Write (read) the start address of Buffer #2 through I/O
Write (read) the end address of Buffer #2 through I/O
Write (read) flow control register.
Write only - clear EOB
and a read when R/W = V
0
-A
2
and I/O pins I/O
1
(1)
and/or EOB
IH
Address Loaded into Buffer
0
. EOB
-
6.42
9
NOTE:
1. Start address and End of address for Buffer #2 and the Flow Control for
also allows reading and clearing the status of the EOB flags. Seven different
CMD cases are available depending on the conditions of A
W. Address bits A
this operation.
1
the corresponding EOB flag and continues from the start address of the
other buffer. In STOP mode, the address pointer stops incrementing after
it reaches the end of the buffer. There is no linear or mask mode available.
/SOB
Buffer Flow Mode
Start Address Buffer #1
End Address Buffer #1
Start Address Buffer #2
End Address Buffer #2
Registered State
Address
EOB Flags
2
flag.
both Buffer #1 and #2, must be programmed as described in the "Buffer
Command Mode" section.
IL
1
for I/O in the input state.
and EOB
DESCRIPTIONS
Register
2
/SOB
3
0
0
0
0
-I/O
-I/O
-A
-I/O
-I/O
Military and Commercial Temperature Ranges
2
11
11
11
are chosen through address A
(1)
11
11
(1)
and data I/O bits I/O
.
.
.
.
Cleared (set at invalid points)
Cleared (set at invalid points)
SCE = V
Cleared to HIGH state
BUFFER CHAINING
12
-I/O
4095 (4K)
Contents
0
-A
15
0
0 (1)
IH
, SR/W = V
2
0
are not used during
while CMD = V
(1,2)
LSB I/O BITS
0
3099 drw 10
-A
IL
2
3099 tbl 15
3099 tbl 16
and R/
IL
and