IDT7005L35G IDT, Integrated Device Technology Inc, IDT7005L35G Datasheet
IDT7005L35G
Specifications of IDT7005L35G
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IDT7005L35G Summary of contents
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... Features True Dual-Ported memory cells which allow simultaneous reads of the same memory location High-speed access – Military: 20/25/35/55/70ns (max.) – Industrial: 35/55ns (max.) – Commercial:15/17/20/25/35/55ns (max.) Low-power operation – IDT7005S Active: 750mW (typ.) Standby: 5mW (typ.) – IDT7005L Active: 700mW (typ.) Standby: 1mW (typ ...
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... This device provides two independent ports with separate control, address, and I/O pins that permit independent, asynchronous access for reads or writes to any location in memory. An automatic power down feature controlled by CE permits the on-chip circuitry of each port to enter a very low standby power mode. ...
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IDT7005S/L High-Speed Dual-Port Static RAM Pin Configurations (1,2,3) 11/19/ 11L 10L ...
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... Package only). 2. 3dV references the interpolated capacitance when the input and output signals switch from from 3V to 0V. Military, Industrial and Commercial Temperature Ranges Outputs I/O 0-7 High-Z Deselected: Power-Down DATA Write to Memory IN DATA Read Memory OUT High-Z Outputs Disabled Outputs I/O 0-7 ...
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IDT7005S/L High-Speed Dual-Port Static RAM DC Electrical Characteristics Over the 0perating Temperature and Supply Voltage Range Symbol Parameter ( Input Leakage Current Output Leakage Current LO V Output Low Voltage OL V ...
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IDT7005S/L High-Speed Dual-Port Static RAM DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range Symbol Parameter Dynamic Operating Current CC , Outputs Disabled IL SEM = V (Both Ports Active) IH ...
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IDT7005S/L High-Speed Dual-Port Static RAM AC Test Conditions Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load AC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range Symbol Parameter READ ...
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IDT7005S/L High-Speed Dual-Port Static RAM Waveform of Read Cycles ADDR CE OE R/W DATA OUT BUSY OUT NOTES: 1. Timing depends on which signal is asserted last CE. 2. Timing depends on which signal is ...
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IDT7005S/L High-Speed Dual-Port Static RAM AC Electrical Characteristics Over the Operating Temperature and Supply Voltage Symbol Parameter WRITE CYCLE t Write Cycle Time WC (3) t Chip Enable to End-of-Write EW t Address Valid to End-of-Write AW ...
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... access RAM SEM = V To access semaphore and . IH IL Military, Industrial and Commercial Temperature Ranges ( ( ( LOW CE and a LOW R/W for memory array writing cycle and SEM = 6.42 10 (1,5, (1,5) ( allow the I/O drivers to turn off and data to be placed WZ DW must be met for either condition ...
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IDT7005S/L High-Speed Dual-Port Static RAM Timing Waveform of Semaphore Read after Write Timing, Either Side VALID ADDRESS SEM DATA R/W OE Write Cycle NOTE ...
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IDT7005S/L High-Speed Dual-Port Static RAM AC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range Symbol Parameter BUSY TIMING (M/S BUSY Access Time from Address Match t BAA BUSY Disable Time from Address Not ...
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IDT7005S/L High-Speed Dual-Port Static RAM Timing Waveform of Write with Port-to-Port Read with BUSY (M (4) IH ADDR "A" R/W "A" DATA IN "A" (1) t APS ADDR "B" BUSY "B" DATA OUT "B" ...
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IDT7005S/L High-Speed Dual-Port Static RAM Waveform of BUSY Arbitration Controlled by CE Timing ADDR "A" and "B" CE "A" (2) t APS CE "B" BUSY "B" Waveform of BUSY Arbitration Cycle Controlled by Address Match Timing (M/S ...
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IDT7005S/L High-Speed Dual-Port Static RAM Waveform of Interrupt Timing ADDR "A" ( "A" R/W "A" INT "B" ADDR "B" "B" OE "B" INT "B" NOTES: 1. All timing is the same ...
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... The message (8 bits) at 1FFE or 1FFF is user-defined, since addressable SRAM location. If the interrupt function is not used, address locations 1FFE and 1FFF are not used as mail boxes, but as part of the random access memory. Refer to Truth Table III for the interrupt operation. 6.42 ...
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IDT7005S/L High-Speed Dual-Port Static RAM BUSY (L) Figure 3. Busy and chip enable routing for both width and depth expansion with IDT7005 RAMs. Busy Logic Busy Logic provides a hardware indication that both ports of the RAM ...
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... IDT7005’s Dual-Port RAM. Say the RAM was to be divided into two blocks which were to be dedicated at any one time to servicing either the left or right port. Semaphore 0 could be used to indicate the side which would control the lower section of memory, and 6.42 18 ...
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... Semaphores are a useful form of arbitration in systems like disk interfaces where the CPU must be locked out of a section of memory during a transfer and the I/O device cannot tolerate any wait states. With the use of semaphores, once the two devices has determined which memory area was “ ...
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IDT7005S/L High-Speed Dual-Port Static RAM Ordering Information XXXXX A 999 A Device Power Speed Package Type NOTES: 1. Industrial temperature range is available on selected TQFP packages in standard power. For other speeds, packages and powers contact ...