IDT7005L35G IDT, Integrated Device Technology Inc, IDT7005L35G Datasheet - Page 16

• Manufacturer Part Number: IDT7005L35G
• Description: IC SRAM 64KBIT 35NS 68PGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT7005L35G

• Format - Memory: RAM
• Memory Type: SRAM - Dual Port, Asynchronous
• Memory Size: 64K (8K x 8)
• Speed: 35ns
• Interface: Parallel
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 68-PGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 7005L35G

Truth Table IV — Address BUSY
Arbitration
NOTES:
1. Pins BUSY
2. 'L' if the inputs to the opposite port were stable prior to the address and enable inputs of this port. 'H' if the inputs to the opposite port became stable after the address
3. Writes to the left port are internally ignored when BUSY
Truth Table V — Example of Semaphore Procurement Sequence
Functional Description
I/O pins that permit independent access for reads or writes to any location
in memory. The IDT7005 has an automatic power down feature controlled
by CE. The CE controls on-chip power down circuitry that permits the
respective port to go into a standby mode when not selected (CE HIGH).
When a port is enabled, access to the entire memory array is permitted.
Interrupts
or message center) is assigned to each port. The left port interrupt flag
(INT
NOTES:
1. This table denotes a sequence of events for only one of the eight semaphores on the IDT7005.
2. There are eight semaphore flags written to via I/O
3. CE=V
No Action
Left Port Writes "0" to Semaphore
Right Port Writes "0" to Semaphore
Left Port Writes "1" to Semaphore
Left Port Writes "0" to Semaphore
Right Port Writes "1" to Semaphore
Left Port Writes "1" to Semaphore
Right Port Writes "0" to Semaphore
Right Port Writes "1" to Semaphore
Left Port Writes "0" to Semaphore
Left Port Writes "1" to Semaphore
CE
IDT7005S/L
High-Speed 8K x 8 Dual-Port Static RAM
X
H
X
L
push-pull, not open drain outputs. On slaves the BUSY
and enable inputs of this port. If t
when BUSY
The IDT7005 provides two ports with separate control, address and
If the user chooses the interrupt function, a memory location (mail box
L
L
) is asserted when the right port writes to memory location 1FFE
IH
CE
, SEM=V
X
X
H
L
R
L
Inputs
R
and BUSY
outputs are driving LOW regardless of actual logic level on the pin.
Functions
NO MATCH
IL
A
A
MATCH
MATCH
MATCH
to access the semaphores. Refer to the semaphore Read/Write Control Truth Table.
OR
OL
-A
-A
R
12L
12R
are both outputs when the part is configured as a master. Both are inputs when configured as a slave. BUSY
APS
BUSY
is not met, either BUSY
(2)
H
H
H
L
Outputs
(1)
D
BUSY
0
0
- D
(2)
and read from all I/O
H
H
H
L
1
0
1
1
0
1
1
1
0
1
0
7
outputs are driving LOW regardless of actual logic level on the pin. Writes to the right port are internally ignored
R
X
Left
(1)
input internally inhibits writes.
L
or BUSY
Write Inhibit
Function
Normal
Normal
Normal
D
0
R
2738 tbl 18
- D
= LOW will result. BUSY
's
. These eight semaphores are addressed by A
7
1
1
1
1
1
1
1
(3)
1
0
0
0
6.42
Right
16
(HEX), where a write is defined as CE = R/W= V
The left port clears the interrupt through access of address location 1FFE
when CE = OE = V
the right port interrupt flag (INT
memory location 1FFF (HEX) and to clear the interrupt flag (INT
right port must read the memory location 1FFF. The message (8 bits) at
1FFE or 1FFF is user-defined, since it is an addressable SRAM location.
If the interrupt function is not used, address locations 1FFE and 1FFF are
not used as mail boxes, but as part of the random access memory. Refer
to Truth Table III for the interrupt operation.
Semaphore free
Left port has semaphore token
No change. Right side has no write access to semaphore
Right port obtains semaphore token
No change. Left port has no write access to semaphore
Left port obtains semaphore token
Semaphore free
Right port has semaphore token
Semaphore free
Left port has semaphore token
Semaphore free
Military, Industrial and Commercial Temperature Ranges
L
and BUSY
IL.
For this example, R/W is a "don't care". Likewise,
R
outputs can not be LOW simultaneously.
R
) is asserted when the left port writes to
Status
0
- A
2
.
X
outputs on the IDT7005 are
IL
per Truth Table III.
(1,2,3)
2738 tbl 19
R
), the