IDT7005L35G IDT, Integrated Device Technology Inc, IDT7005L35G Datasheet - Page 17

• Manufacturer Part Number: IDT7005L35G
• Description: IC SRAM 64KBIT 35NS 68PGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT7005L35G

• Format - Memory: RAM
• Memory Type: SRAM - Dual Port, Asynchronous
• Memory Size: 64K (8K x 8)
• Speed: 35ns
• Interface: Parallel
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 68-PGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 7005L35G

Busy Logic
have accessed the same location at the same time. It also allows one of the
two accesses to proceed and signals the other side that the RAM is “busy”.
The BUSY pin can then be used to stall the access until the operation on
the other side is completed. If a write operation has been attempted from
the side that receives a BUSY indication, the write signal is gated internally
to prevent the write from proceeding.
In some cases it may be useful to logically OR the BUSY outputs together
and use any BUSY indication as an interrupt source to flag the event of
an illegal or illogical operation. If the write inhibit function of BUSY logic is
not desirable, the BUSY logic can be disabled by placing the part in slave
mode with the M/S pin. Once in slave mode the BUSY pin operates solely
as a write inhibit input pin. Normal operation can be programmed by tying
the BUSY pins HIGH. If desired, unintended write operations can be
prevented to a port by tying the BUSY pin for that port LOW.
pull type outputs and do not require pull up resistors to operate. If these
RAMs are being expanded in depth, then the BUSY indication for the
resulting array requires the use of an external AND gate.
Width Expansion with Busy Logic
Master/Slave Arrays
logic, one master part is used to decide which side of the RAM array will
receive a BUSY indication, and to output that indication. Any number of
slaves to be addressed in the same address range as the master, use the
BUSY signal as a write inhibit signal. Thus on the IDT7005 RAM the BUSY
pin is an output if the part is used as a master (M/S pin = V
pin is an input if the part used as a slave (M/S pin = V
Figure 3.
decision could result with one master indicating BUSY on one side of the
array and another master indicating BUSY on one other side of the array.
This would inhibit the write operations from one port for part of a word and
inhibit the write operations from the other port for the other part of the word.
IDT7005S/L
High-Speed 8K x 8 Dual-Port Static RAM
Busy Logic provides a hardware indication that both ports of the RAM
The use of BUSY logic is not required or desirable for all applications.
The BUSY outputs on the IDT 7005 RAM in master mode, are push-
When expanding an IDT7005 RAM array in width while using BUSY
If two or more master parts were used when expanding in width, a split
The BUSY arbitration on a master is based on the chip enable and
Figure 3. Busy and chip enable routing for both width and depth expansion with IDT7005 RAMs.
BUSY (L)
BUSY (L)
MASTER
Dual Port
RAM
BUSY (L)
MASTER
Dual Port
RAM
IH
), and the BUSY
IL
) as shown in
BUSY (R)
BUSY (R)
CE
CE
6.42
17
address signals only. It ignores whether an access is a read or write.
this timing can result in a glitched internal write inhibit signal and corrupted
data in the slave.
Semaphores
with an additional 8 address locations dedicated to binary semaphore flags.
These flags allow either processor on the left or right side of the Dual-Port
RAM to claim a privilege over the other processor for functions defined by
the system designer’s software. As an example, the semaphore can be
used by one processor to inhibit the other from accessing a portion of the
Dual-Port RAM or any other shared resource.
completely independent of each other. This means that the activity on the
left port in no way slows the access time of the right port. Both ports are
identical in function to standard CMOS Static RAM and can be read from,
or written to, at the same time with the only possible conflict arising from the
simultaneous writing of, or a simultaneous READ/WRITE of, a non-
semaphore location. Semaphores are protected against such ambiguous
situations and may be used by the system program to avoid any conflicts
in the non-semaphore portion of the Dual-Port RAM. These devices have
an automatic power-down feature controlled by CE, the Dual-Port RAM
enable, and SEM, the semaphore enable. The CE and SEM pins control
on-chip power down circuitry that permits the respective port to go into
standby mode when not selected. This is the condition which is shown in
Truth Table I where CE and SEM are both HIGH.
or controllers and are typically very high-speed systems which are
software controlled or software intensive. These systems can benefit from
a performance increase offered by the IDT7005's hardware semaphores,
which provide a lockout mechanism without requiring complex program-
ming.
system flexibility by permitting shared resources to be allocated in varying
actual write pulse can be initiated with the R/W signal. Failure to observe
In a master/slave array, both address and chip enable must be valid
long enough for a BUSY flag to be output from the master before the
BUSY (L)
BUSY (L)
SLAVE
Dual Port
RAM
SLAVE
Dual Port
RAM
The IDT7005 is an extremely fast Dual-Port 8K x 8 CMOS Static RAM
The Dual-Port RAM features a fast access time, and both ports are
Systems which can best use the IDT7005 contain multiple processors
Software handshaking between processors offers the maximum in
Military, Industrial and Commercial Temperature Ranges
BUSY (R)
BUSY (R)
CE
CE
BUSY (R)
2738 drw 19
,