UPD44164362AF5-E33-EQ2 Renesas Electronics America, UPD44164362AF5-E33-EQ2 Datasheet
UPD44164362AF5-E33-EQ2
Specifications of UPD44164362AF5-E33-EQ2
Related parts for UPD44164362AF5-E33-EQ2
UPD44164362AF5-E33-EQ2 Summary of contents
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... Description μ The PD44164082A 2,097,152-word by 8-bit, the μ PD44164182A 1,048,576-word by 18-bit and the double data rate static RAM fabricated with advanced CMOS technology using full CMOS six-transistor memory cell. μ μ The PD44164082A-A, PD44164092A-A, peripheral circuitry and a burst counter. All input registers controlled by an input clock pair (K and K#) are latched on the positive edge of K and K# ...
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PD44164082A-A, 44164092A-A, 44164182A-A, 44164362A-A Ordering Information (1) Operating Ambient Temperature T Part number Cycle Time ns μ PD44164082AF5-E33-EQ2-A 3.3 μ PD44164082AF5-E40-EQ2-A 4.0 μ PD44164082AF5-E50-EQ2-A 5.0 μ PD44164092AF5-E33-EQ2-A 3.3 μ PD44164092AF5-E40-EQ2-A 4.0 μ PD44164092AF5-E50-EQ2-A 5.0 μ PD44164182AF5-E33-EQ2-A 3.3 μ PD44164182AF5-E37-EQ2-A ...
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PD44164082A-A, 44164092A-A, 44164182A-A, 44164362A-A (2) Operating Ambient Temperature T Part number Cycle Time ns μ PD44164082AF5-E37Y-EQ2-A 3.7 μ PD44164082AF5-E40Y-EQ2-A 4.0 μ PD44164082AF5-E50Y-EQ2-A 5.0 μ PD44164092AF5-E37Y-EQ2-A 3.7 μ PD44164092AF5-E40Y-EQ2-A 4.0 μ PD44164092AF5-E50Y-EQ2-A 5.0 μ PD44164182AF5-E37Y-EQ2-A 3.7 μ PD44164182AF5-E40Y-EQ2-A 4.0 μ ...
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PD44164082A-A, 44164092A-A, 44164182A-A, 44164362A-A Pin Configurations CQ DQ4 ...
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PD44164082A-A, 44164092A-A, 44164182A-A, 44164362A CQ DQ5 ...
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PD44164082A-A, 44164092A-A, 44164182A-A, 44164362A CQ DQ9 DQ10 DQ11 DQ12 NC V ...
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PD44164082A-A, 44164092A-A, 44164182A-A, 44164362A CQ DQ27 DQ18 DQ28 DQ29 DQ19 DQ20 DQ30 DQ21 V ...
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PD44164082A-A, 44164092A-A, 44164182A-A, 44164362A-A Pin Identification Symbol A0 Synchronous Address Inputs: These inputs are registered and must meet the setup and hold times around the A rising edge of K. All transactions operate on a burst of two words ...
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PD44164082A-A, 44164092A-A, 44164182A-A, 44164362A-A Symbol CQ, CQ# Synchronous Echo Clock Outputs. The rising edges of these outputs are tightly matched to the synchronous data outputs and can be used as a data valid indication. These signals run freely and ...
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... PD44164082A-A, 44164092A-A, 44164182A-A, 44164362A-A Block Diagram CLK A0 Address Address Register LD# E Compare Write address K Register E Input Register E K# Input Register W#` Register E 10 Burst Logic A0 A0'' Output control Logic A0' /A0' A0' Memory CLK K Array /A0' A0 A0''' Output Enable Register C Data Sheet M19866EJ1V0DS A0''' MUX 1 Output Buffer DQ E ...
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PD44164082A-A, 44164092A-A, 44164182A-A, 44164362A-A Power-on Sequence The following two timing charts show the recommended power-on sequence, i.e., when starting the clock after stable and when starting the clock before Clock starts after ...
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PD44164082A-A, 44164092A-A, 44164182A-A, 44164362A-A 2. Clock starts before stable DD DD The clock is supplied from a clock generator. ( DLL# Clock Unstable Clock (level, frequency) Clock Start ( ...
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PD44164082A-A, 44164092A-A, 44164182A-A, 44164362A-A Burst Sequence Linear Burst Sequence Table μ μ [ PD44164182A-A, PD44164362A-A] A0 External Address 0 1st Internal Burst Address 1 Truth Table Operation LD WRITE cycle L Load address, input write data on ...
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PD44164082A-A, 44164092A-A, 44164182A-A, 44164362A-A Byte Write Operation μ [ PD44164082A-A] Operation K L → H Write DQ0 to DQ7 – L → H Write DQ0 to DQ3 – Write DQ4 to DQ7 L → H – Write nothing L ...
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PD44164082A-A, 44164092A-A, 44164182A-A, 44164362A-A μ [ PD44164362A-A] Operation K L → H Write DQ0 to DQ35 – L → H Write DQ0 to DQ8 – L → H Write DQ9 to DQ17 – Write DQ18 to DQ26 L → ...
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PD44164082A-A, 44164092A-A, 44164182A-A, 44164362A-A Bus Cycle State Diagram Load, Count = 2 READ DOUBLE Count = Count + 2 NOP, Count = 2 Supply voltage provided Power UP Remarks internally advanced in accordance with the burst ...
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PD44164082A-A, 44164092A-A, 44164182A-A, 44164362A-A Electrical Specifications Absolute Maximum Ratings Parameter Symbol Supply voltage V DD Output supply voltage V DD Input voltage V IN Input / Output voltage V I/O Operating ambient temperature T A Storage temperature T stg ...
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PD44164082A-A, 44164092A-A, 44164182A-A, 44164362A-A DC Characteristics (V = 1.8 ± 0 Parameter Symbol Input leakage current I LI I/O leakage current I LO Operating supply I Note1 Commercial DD current (T (Read cycle/ Write cycle) Industrial (T ...
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PD44164082A-A, 44164092A-A, 44164182A-A, 44164362A-A AC Characteristics (V = 1.8 ± 0 Test Conditions (V = 1.8 ± 0 Input waveform (Rise / Fall time ≤ 0.3 ns) 1.25 V 0.75 V 0.25 V ...
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PD44164082A-A, 44164092A-A, 44164182A-A, 44164362A-A Read and Write Cycle Parameter Clock Average Clock cycle time (K, K#, C, C#) Clock phase jitter (K, K#, C, C#) Clock HIGH time (K, K#, C, C#) Clock LOW time (K, K#, C, C#) ...
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PD44164082A-A, 44164092A-A, 44164182A-A, 44164362A-A Notes 1. When debugging the system or board, these products can operate at a clock frequency slower than TKHKH (MAX.) without the DLL/PLL circuit being used, if DLL# = LOW. Read latency (RL) is changed ...
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PD44164082A-A, 44164092A-A, 44164182A-A, 44164362A-A Read and Write Timing NOP READ (burst of 2) (burst TKHKH K TKHKL TKLKH TKLKH TKHK#H K# LD# TIVKH TKHIX R, W# TAVKH TKHAX Address Qx2 TCHQX1 ...
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PD44164082A-A, 44164092A-A, 44164182A-A, 44164362A-A Application Example SRAM LD BWx# C/C# K/ SRAM Controller R Data IO Address LD BW# SRAM#1 CQ/CQ SRAM#4 CQ/CQ Source CLK/CLK# ...
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PD44164082A-A, 44164092A-A, 44164182A-A, 44164362A-A JTAG Specification These products support a limited set of JTAG functions as in IEEE standard 1149.1. Test Access Port (TAP) Pins Pin name Pin assignments Test Clock Input. All input are captured on the rising ...
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PD44164082A-A, 44164092A-A, 44164182A-A, 44164362A-A JTAG AC Test Conditions Input waveform (Rise / Fall time ≤ 1 ns) 1 Output waveform 0.9 V Output load Test Points Test Points Figure 2. External load at test ...
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PD44164082A-A, 44164092A-A, 44164182A-A, 44164362A-A JTAG AC Characteristics Parameter Symbol Clock Clock cycle time t THTH Clock frequency f TF Clock HIGH time t THTL Clock LOW time t TLTH Output time TCK LOW to TDO unknown t TLOX TCK ...
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PD44164082A-A, 44164092A-A, 44164182A-A, 44164362A-A Scan Register Definition (1) Register name Instruction register The instruction register holds the instructions that are executed by the TAP controller when it is moved into the run-test/idle or the various data register state. The ...
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PD44164082A-A, 44164092A-A, 44164182A-A, 44164362A-A SCAN Exit Order Bit Signal name Bump no x18 x36 ...
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PD44164082A-A, 44164092A-A, 44164182A-A, 44164362A-A JTAG Instructions Instructions EXTEST The EXTEST instruction allows circuitry external to the component package to be tested. Boundary- scan register cells at output pins are used to apply test vectors, while those at input pins ...
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PD44164082A-A, 44164092A-A, 44164182A-A, 44164362A-A Output Pin States of CQ, CQ# and DQ Instructions Control-Register Status EXTEST 0 1 IDCODE 0 1 SAMPLE SAMPLE 0 1 BYPASS 0 1 Remark The output pin statuses during each instruction vary ...
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PD44164082A-A, 44164092A-A, 44164182A-A, 44164362A-A Boundary Scan Register Status of Output Pins CQ, CQ# and DQ Instructions SRAM Status EXTEST READ (Low-Z) NOP (High-Z) IDCODE READ (Low-Z) NOP (High-Z) SAMPLE-Z READ (Low-Z) NOP (High-Z) SAMPLE READ (Low-Z) NOP (High-Z) BYPASS ...
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PD44164082A-A, 44164092A-A, 44164182A-A, 44164362A-A TAP Controller State Diagram 1 Test-Logic-Reset Run-Test / Idle Disabling the Test Access Port It is possible to use this device without utilizing the TAP. To disable the TAP Controller without interfering ...
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PD44164082A-A, 44164092A-A, 44164182A-A, 44164362A-A Run-Test/Idle Update-IR Exit1-IR Shift-IR Exit2-IR Pause-IR Exit1-IR Shift-IR Capture-IR Select-IR-Scan Select-DR-Scan Run-Test/Idle Test-Logic-Reset Data Sheet M19866EJ1V0DS 33 ...
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PD44164082A-A, 44164092A-A, 44164182A-A, 44164362A-A 34 Test-Logic-Reset Select-IR-Scan Select-DR-Scan Run-Test/Idle Update-DR Exit1-DR Shift-DR Exit2-DR Pause-DR Exit1-DR Shift-DR Capture-DR Select-DR-Scan Run-Test/Idle Data Sheet M19866EJ1V0DS ...
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PD44164082A-A, 44164092A-A, 44164182A-A, 44164362A-A Package Drawing 165-PIN PLASTIC BGA (13x15) E INDEX MARK φ φ ...
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PD44164082A-A, 44164092A-A, 44164182A-A, 44164362A-A Recommended Soldering Condition Please consult with our sales offices for soldering conditions of these products. Types of Surface Mount Devices μ PD44164082AF5-EQ2-A : 165-pin PLASTIC BGA (13 x 15) μ PD44164092AF5-EQ2-A : 165-pin PLASTIC BGA ...
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PD44164082A-A, 44164092A-A, 44164182A-A, 44164362A-A [ MEMO ] Data Sheet M19866EJ1V0DS 37 ...
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PD44164082A-A, 44164092A-A, 44164182A-A, 44164362A-A [ MEMO ] 38 Data Sheet M19866EJ1V0DS ...
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PD44164082A-A, 44164092A-A, 44164182A-A, 44164362A-A NOTES FOR CMOS DEVICES 1 VOLTAGE APPLICATION WAVEFORM AT INPUT PIN Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area ...
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PD44164082A-A, 44164092A-A, 44164182A-A, 44164362A-A • The information in this document is current as of July, 2009. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets, etc., for ...