UPD44164362AF5-E33-EQ2 Renesas Electronics America, UPD44164362AF5-E33-EQ2 Datasheet - Page 30

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UPD44164362AF5-E33-EQ2

Manufacturer Part Number
UPD44164362AF5-E33-EQ2
Description
SRAM DDRII 18MBIT CIO 165-PBGA
Manufacturer
Renesas Electronics America
Datasheet

Specifications of UPD44164362AF5-E33-EQ2

Format - Memory
RAM
Memory Type
SRAM - Synchronous, DDR II
Memory Size
18M (512K x 36)
Speed
300MHz
Interface
Parallel
Voltage - Supply
1.7 V ~ 1.9 V
Operating Temperature
0°C ~ 70°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Output Pin States of CQ, CQ# and DQ
Remark
30
EXTEST
IDCODE
SAMPLE-Z
SAMPLE
BYPASS
Instructions
The output pin statuses during each instruction vary according
to the Control-Register status (value of Boundary Scan
Register, bit no. 48).
There are three statuses:
The Control-Register status is set during Update-DR at the
EXTEST or SAMPLE instruction.
Update : Contents of the “Update Register” are output to
SRAM : Contents of the SRAM internal output “SRAM
High-Z : The output pin (QDR Pad) becomes high
the output pin (QDR Pad).
Output” are output to the output pin (QDR Pad).
ctrl”.
impedance by controlling of the “High-Z JTAG
Control-Register Status
μ
PD44164082A-A, 44164092A-A, 44164182A-A, 44164362A-A
0
1
0
1
0
1
0
1
0
1
Data Sheet M19866EJ1V0DS
CQ, CQ#
Update
Update
High-Z
High-Z
SRAM
SRAM
SRAM
SRAM
SRAM
SRAM
Output Pin Status
Update
High-Z
High-Z
High-Z
SRAM
SRAM
SRAM
SRAM
SRAM
SRAM
DQ
QDR
Pad
Boundary Scan
Register
High-Z
Update
CAPTURE
Register
Register
Update
JTAG ctrl
High-Z
Output
SRAM
Driver
SRAM
SRAM
Output

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