UPD44164362AF5-E33-EQ2 Renesas Electronics America, UPD44164362AF5-E33-EQ2 Datasheet - Page 27

• Manufacturer Part Number: UPD44164362AF5-E33-EQ2
• Description: SRAM DDRII 18MBIT CIO 165-PBGA
• Manufacturer: Renesas Electronics America

Specifications of UPD44164362AF5-E33-EQ2

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous, DDR II
• Memory Size: 18M (512K x 36)
• Speed: 300MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Scan Register Definition (1)
Scan Register Definition (2)
ID Register Definition
Instruction register
Bypass register
ID register
Boundary register
Instruction register
Bypass register
ID register
Boundary register
μ
μ
μ
μ
PD44164082A-A
PD44164092A-A
PD44164182A-A
PD44164362A-A
Part number
Register name
Register name
Organization ID [31:28] vendor revision no.
512K x 36
1M x 18
The instruction register holds the instructions that are executed by the TAP controller when it is
moved into the run-test/idle or the various data register state. The register can be loaded when it is
placed between the TDI and TDO pins. The instruction register is automatically preloaded with the
IDCODE instruction at power-up whenever the controller is placed in test-logic-reset state.
The bypass register is a single bit register that can be placed between TDI and TDO. It allows serial
test data to be passed through the RAMs TAP to another device in the scan chain with as little delay
as possible.
The ID Register is a 32 bit register that is loaded with a device and vendor specific 32 bit code when
the controller is put in capture-DR state with the IDCODE command loaded in the instruction register.
The register is then placed between the TDI and TDO pins when the controller is moved into shift-DR
state.
The boundary register, under the control of the TAP controller, is loaded with the contents of the
RAMs I/O ring when the controller is in capture-DR state and then is placed between the TDI and
TDO pins when the controller is moved to shift-DR state. Several TAP instructions can be used to
activate the boundary register.
The Scan Exit Order tables describe which device bump connects to each boundary register
location. The first column defines the bit’s position in the boundary register. The second column is
the name of the input or I/O at the bump and the third column is the bump number.
2M x 8
2M x 9
μ
PD44164082A-A, 44164092A-A, 44164182A-A, 44164362A-A
Bit size
107
32
3
1
Data Sheet M19866EJ1V0DS
XXXX
XXXX
XXXX
XXXX
Unit
bit
bit
bit
bit
0000 0000 0001 0010
0000 0000 0101 0011
0000 0000 0001 0011
0000 0000 0001 0100
Description
ID [27:12] part no.
ID [11:1] vendor ID no. ID [0] fix bit
00000010000
00000010000
00000010000
00000010000
1
1
1
1
27