UPD44164362AF5-E33-EQ2 Renesas Electronics America, UPD44164362AF5-E33-EQ2 Datasheet - Page 9

• Manufacturer Part Number: UPD44164362AF5-E33-EQ2
• Description: SRAM DDRII 18MBIT CIO 165-PBGA
• Manufacturer: Renesas Electronics America

Specifications of UPD44164362AF5-E33-EQ2

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous, DDR II
• Memory Size: 18M (512K x 36)
• Speed: 300MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

CQ, CQ#
ZQ
DLL#
TMS
TDI
TCK
TDO
V
V
V
V
NC
REF
DD
DD
SS
Symbol
Q
Synchronous Echo Clock Outputs. The rising edges of these outputs are tightly matched to the synchronous
data outputs and can be used as a data valid indication. These signals run freely and do not stop when DQ
tristates. If C and C# are stopped (if K and K# are stopped in the single clock mode), CQ and CQ# will also
stop.
Output Impedance Matching Input: This input is used to tune the device outputs to the system data bus
impedance. DQ, CQ and CQ# output impedance are set to 0.2 x RQ, where RQ is a resistor from this bump to
ground. The output impedance can be minimized by directly connect ZQ to V
connected directly to GND or left unconnected. The output impedance is adjusted every 1,024 cycles upon
power-up to account for drifts in supply voltage and temperature. After replacement for a resistor, the new
output impedance is reset by implementing power-on sequence.
DLL/PLL Disable: When debugging the system or board, the operation can be performed at a clock frequency
slower than TKHKH (MAX.) without the DLL/PLL circuit being used, if DLL# = LOW. The AC/DC characteristics
cannot be guaranteed. For normal operation, DLL# must be HIGH and it can be connected to V
10 kΩ or less resistor.
IEEE 1149.1 Test Inputs: 1.8 V I/O level. These balls may be left Not Connected if the JTAG function is not
used in the circuit.
IEEE 1149.1 Clock Input: 1.8 V I/O level. This pin must be tied to V
circuit.
IEEE 1149.1 Test Output: 1.8 V I/O level.
HSTL Input Reference Voltage: Nominally V
Power Supply: 1.8 V nominal. See Recommended DC Operating Conditions and DC Characteristics for
range.
Power Supply: Isolated Output Buffer Supply. Nominally 1.5 V. 1.8 V is also permissible. See Recommended
DC Operating Conditions and DC Characteristics for range.
Power Supply: Ground
No Connect: These signals are not connected internally.
μ
PD44164082A-A, 44164092A-A, 44164182A-A, 44164362A-A
Data Sheet M19866EJ1V0DS
DD
Q/2. Provides a reference voltage for the input buffers.
Description
SS
if the JTAG function is not used in the
DD
Q. This pin cannot be
DD
Q through a
(2/2)
9