MT41J64M16LA-15E:B TR Micron Technology Inc, MT41J64M16LA-15E:B TR Datasheet - Page 159
![IC DDR3 SDRAM 1GBIT 96FBGA](/photos/7/23/72317/mfg557-60-fbga_sml.jpg)
MT41J64M16LA-15E:B TR
Manufacturer Part Number
MT41J64M16LA-15E:B TR
Description
IC DDR3 SDRAM 1GBIT 96FBGA
Manufacturer
Micron Technology Inc
Type
DDR3 SDRAMr
Specifications of MT41J64M16LA-15E:B TR
Format - Memory
RAM
Memory Type
DDR3 SDRAM
Memory Size
1G (64M x 16)
Speed
667MHz
Interface
Parallel
Voltage - Supply
1.425 V ~ 1.575 V
Operating Temperature
0°C ~ 95°C
Package / Case
96-FBGA
Organization
64Mx16
Density
1Gb
Address Bus
16b
Maximum Clock Rate
1.333GHz
Operating Supply Voltage (typ)
1.5V
Package Type
FBGA
Operating Temp Range
0C to 95C
Operating Supply Voltage (max)
1.575V
Operating Supply Voltage (min)
1.425V
Supply Current
355mA
Pin Count
96
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf – Rev. J 05/10 EN
DQS to DQ output timing is shown in Figure 78 (page 160). The DQ transitions be-
tween valid data outputs must be within
DQS must also maintain a minimum HIGH and LOW time of
the READ preamble, the DQ balls either will be floating or terminated depending on the
status of the ODT signal.
Figure 79 (page 161) shows the strobe-to-clock timing during a READ. The crossing
point DQS, DQS# must transition within ±
out has no timing relationship to clock, only to DQS, as shown in Figure 79 (page 161).
Figure 79 (page 161) also shows the READ preamble and postamble. Typically, both
DQS and DQS# are High-Z to save power (V
DQS is driven LOW and DQS# is HIGH for
The READ postamble,
ing the READ postamble, DQS is driven LOW and DQS# is HIGH. When complete, the
DQ will either be disabled or will continue terminating depending on the state of the
ODT signal. Figure 84 (page 165) demonstrates how to measure
t
RPST, is one half clock from the last DQS, DQS# transition. Dur-
159
Micron Technology, Inc. reserves the right to change products or specifications without notice.
t
DQSQ of the crossing point of DQS, DQS#.
t
t
DQSCK of the clock crossing point. The data
RPRE. This is known as the READ preamble.
DDQ
1Gb: x4, x8, x16 DDR3 SDRAM
). Prior to data output from the DRAM,
t
© 2006 Micron Technology, Inc. All rights reserved.
QSH and
t
RPST.
t
QSL. Prior to
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