MT41J64M16LA-15E:B TR Micron Technology Inc, MT41J64M16LA-15E:B TR Datasheet - Page 161
![IC DDR3 SDRAM 1GBIT 96FBGA](/photos/7/23/72317/mfg557-60-fbga_sml.jpg)
MT41J64M16LA-15E:B TR
Manufacturer Part Number
MT41J64M16LA-15E:B TR
Description
IC DDR3 SDRAM 1GBIT 96FBGA
Manufacturer
Micron Technology Inc
Type
DDR3 SDRAMr
Specifications of MT41J64M16LA-15E:B TR
Format - Memory
RAM
Memory Type
DDR3 SDRAM
Memory Size
1G (64M x 16)
Speed
667MHz
Interface
Parallel
Voltage - Supply
1.425 V ~ 1.575 V
Operating Temperature
0°C ~ 95°C
Package / Case
96-FBGA
Organization
64Mx16
Density
1Gb
Address Bus
16b
Maximum Clock Rate
1.333GHz
Operating Supply Voltage (typ)
1.5V
Package Type
FBGA
Operating Temp Range
0C to 95C
Operating Supply Voltage (max)
1.575V
Operating Supply Voltage (min)
1.425V
Supply Current
355mA
Pin Count
96
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Figure 79: Data Strobe Timing – READs
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf – Rev. J 05/10 EN
early strobe
DQS, DQS#
DQS, DQS#
late strobe
CK#
CK
t LZ (DQS) MIN
T0
t LZ (DQS) MAX
t RPRE
t
parameters are referenced to a specific voltage level which specifies when the device
output is no longer driving
(DQ). Figure 80 (page 162) shows a method to calculate the point when the device is no
longer driving
ing the signal at two different voltages. The actual voltage measurement points are not
critical as long as the calculation is consistent. The parameters
(DQS), and
HZ and
t DQSCK (MIN)
t RPRE
Bit 0
RL measured
to this point
t
LZ transitions occur in the same access time as valid data transitions. These
T1
t QSH
t DQSCK (MAX)
t
HZ (DQ) are defined as single-ended.
Bit 0
Bit 1
t
HZ (DQS) and
t QSH
t DQSCK (MIN)
t QSL
Bit 1
Bit 2
t QSL
T2
t QSH
t DQSCK (MAX)
t
HZ (DQS) and
Bit 2
161
Bit 3
t
HZ (DQ) or begins driving
t QSH
t DQSCK (MIN)
t QSL
Bit 4
Bit 3
Micron Technology, Inc. reserves the right to change products or specifications without notice.
t QSL
T3
t DQSCK (MAX)
t
HZ (DQ) or begins driving
Bit 4
Bit 5
1Gb: x4, x8, x16 DDR3 SDRAM
t DQSCK (MIN)
Bit 5
Bit 6
T4
t
t DQSCK (MAX)
LZ (DQS),
Bit 6
Bit 7
© 2006 Micron Technology, Inc. All rights reserved.
t HZ (DQS) MIN
t RPST
t
LZ (DQS),
Bit 7
t
LZ (DQ) by measur-
t
t RPST
LZ (DQS),
T5
t HZ (DQS) MAX
t
LZ (DQ),
t
LZ
t
HZ
T6
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