PSD4235G2-90U STMicroelectronics, PSD4235G2-90U Datasheet - Page 102

• Manufacturer Part Number: PSD4235G2-90U
• Description: IC FLASH 4MBIT 90NS 80TQFP
• Manufacturer: STMicroelectronics

Specifications of PSD4235G2-90U

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 4M (512K x 8)
• Speed: 90ns
• Interface: Parallel
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 80-TQFP, 80-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-1968

Programming in-circuit using the JTAG serial interface
23.2
Note:
23.3
102/129
The state of the PSD Reset (RESET) signal does not interrupt (or prevent) JTAG operations
if the JTAG pins are dedicated by an NVM configuration bit (via PSDsoft Express). However,
Reset (RESET) will prevent or interrupt JTAG operations if the JTAG Enable register (as
shown in
The PSD supports JTAG In-System-Programmability (ISP) commands, but not Boundary
Scan. ST’s PSDsoft Express software tool and FlashLINK JTAG programming cable
implement the JTAG In-System-Programmability (ISP) commands.
JTAG extensions
TSTAT and TERR are two JTAG extension signals enabled by a JTAG command received
over the four standard JTAG pins (TMS, TCK, TDI, and TDO). They are used to speed
Program and Erase cycles by indicating status on PSD pins instead of having to scan the
status out serially using the standard JTAG channel. See Application Note AN1153.
TERR indicates if an error has occurred when erasing a sector or programming in Flash
memory. This signal goes low (active) when an Error condition occurs, and stays low until a
specific JTAG command is executed or a Reset (RESET) pulse is received after an
“ISC_DISABLE” command.
TSTAT behaves the same as Ready/Busy (PE4) described in
(PE4). TSTAT is high when the PSD4235G2 device is in READ mode (primary Flash
memory and secondary Flash memory contents can be read). TSTAT is low when Flash
memory Program or Erase cycles are in progress, and also when data is being written to the
secondary Flash memory .
TSTAT and TERR can be configured as open-drain type signals with a JTAG command.
The state of Reset (Reset) does not interrupt (or prevent) JTAG operations if the JTAG
signals are dedicated by an NVM Configuration bit (via PSDsoft Express). However, Reset
(Reset) prevents or interrupts JTAG operations if the JTAG Enable register (as shown in
Table
Security and Flash memory protection
When the Security bit is set, the device cannot be read on a device programmer or through
the JTAG Port. When using the JTAG Port, only a Full Chip Erase command is allowed.
All other Program, Erase and Verify commands are blocked. Full Chip Erase returns the
device to a non-secured blank state. The Security bit can be set in PSDsoft Express.
All primary Flash memory and secondary Flash memory sectors can individually be sector
protected against erasure. The sector protect bits can be set in PSDsoft Express.
Table 52.
21) is used to enable the JTAG signals.
Port E pin
Table
PE0
PE1
PE2
PE3
JTAG port signals
21) is used to enable the JTAG pins.
JTAG signals
TMS
TDO
TCK
TDI
Mode Select
Clock
Serial Data In
Serial Data Out
Section 7.2.2: Ready/Busy
Description
PSD4235G2