CY7C1263V18-375BZXC Cypress Semiconductor Corp, CY7C1263V18-375BZXC Datasheet - Page 6

• Manufacturer Part Number: CY7C1263V18-375BZXC
• Description: IC SRAM 36MBIT 375MHZ 165TFBGA
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1263V18-375BZXC

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous, QDR II
• Memory Size: 36M (4M x 8)
• Speed: 375MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 165-TFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Pin Definitions
Document Number: 001-06366 Rev. *E
D
WPS
NWS
BWS
BWS
A
Q
RPS
QVLD
K
K
[x:0]
[x:0]
Pin Name
0
2
0
, BWS
, BWS
, NWS
1
3
1
,
,
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Valid Output
Outputs-
Indicator
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Clock
Input-
Clock
IO
Data Input Signals. Sampled on the rising edge of K and K clocks during valid write operations.
CY7C1261V18 – D
CY7C1276V18 – D
CY7C1263V18 – D
CY7C1265V18 – D
Write Port Select, Active LOW. Sampled on the rising edge of the K clock. When asserted
active, a write operation is initiated. Deasserting deselects the write port. Deselecting the write
port causes D
Nibble Write Select 0, 1, Active LOW (CY7C1261V18 Only). Sampled on the rising edge of
the K and K clocks when write operations are active . Used to select which nibble is written into
the device during the current portion of the write operations. NWS
controls D
All the Nibble Write Selects are sampled on the same edge as the data. The corresponding
nibble of data is ignored by deselecting a nibble write select and is not written into the device.
Byte Write Select 0, 1, 2, and 3, Active LOW. Sampled on the rising edge of the K and K clocks
during write operations. Used to select which byte is written into the device during the current
portion of the Write operations. Bytes not written remain unaltered.
CY7C1276V18 – BWS
CY7C1263V18 – BWS
CY7C1265V18 – BWS
controls D
All the Byte Write Selects are sampled on the same edge as the data. Deselecting a Byte Write
Select causes the corresponding byte of data to be ignored and not written into the device.
Address Inputs. Sampled on the rising edge of the K clock during active read and write opera-
tions. These address inputs are multiplexed for both read and write operations. Internally, the
device is organized as 4M x 8 (4 arrays each of 1M x 8) for CY7C1261V18, 4M x 9 (4 arrays
each of 1M x 9) for CY7C1276V18, 2M x 18 (4 arrays each of 512K x 18) for CY7C1263V18
and 1M x 36 (4 arrays each of 256K x 36) for
are needed to access the entire memory array of CY7C1261V18 and CY7C1276V18, 19 address
inputs for CY7C1263V18 and 18 address inputs for CY7C1265V18. These inputs are ignored
when the appropriate port is deselected.
Data Output Signals. These pins drive out the requested data during a read operation. Valid
data is driven out on the rising edge of both the K and K clocks during read operations. When
the read port is deselected, Q
CY7C1261V18 – Q
CY7C1276V18 – Q
CY7C1263V18 – Q
CY7C1265V18 – Q
Read Port Select, Active LOW. Sampled on the rising edge of Positive Input Clock (K). When
active, a read operation is initiated. Deasserting causes the read port to be deselected. When
deselected, the pending access is allowed to complete and the output drivers are automatically
tri-stated following the next rising edge of the K clock. Each read access consists of a burst of
four sequential transfers.
Valid Output Indicator. The Q Valid indicates valid output data. QVLD is edge aligned with CQ
and CQ.
Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs to the
device and to drive out data through Q
on the rising edge of K.
Negative Input Clock Input. K is used to capture synchronous inputs being presented to the
device and to drive out data through Q
[7:4]
[35:27]
.
[x:0]
.
to be ignored.
[7:0]
[8:0]
[17:0]
[35:0]
[7:0]
[8:0]
[17:0]
[35:0]
0
0
0
controls D
controls D
controls D
[x:0]
[8:0]
are automatically tri-stated.
[8:0]
[8:0]
, BWS
[x:0]
[x:0]
and BWS
Pin Description
when in single clock mode. All accesses are initiated
when in single clock mode.
1
CY7C1265V18.
controls D
1
controls D
CY7C1261V18, CY7C1276V18
CY7C1263V18, CY7C1265V18
[17:9]
, BWS
[17:9]
Therefore, only 20 address inputs
.
2
controls D
0
controls D
[26:18]
[3:0]
, and BWS
and NWS
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