LTC1421CSW#TR Linear Technology, LTC1421CSW#TR Datasheet - Page 13

IC CONTROLLER HOTSWAP ADJ 24SOIC

LTC1421CSW#TR

Manufacturer Part Number
LTC1421CSW#TR
Description
IC CONTROLLER HOTSWAP ADJ 24SOIC
Manufacturer
Linear Technology
Type
Hot-Swap Controllerr
Datasheet

Specifications of LTC1421CSW#TR

Applications
General Purpose
Internal Switch(s)
No
Voltage - Supply
3 V ~ 12 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
24-SOIC (0.300", 7.50mm Width)
Linear Misc Type
Positive Low Voltage
Family Name
LTC1421
Package Type
SOIC W
Operating Supply Voltage (min)
3V
Operating Supply Voltage (max)
12V
Operating Temperature (min)
0C
Operating Temperature (max)
70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
24
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LTC1421CSW#TRLTC1421CSW
Manufacturer:
ROHM
Quantity:
7
Company:
Part Number:
LTC1421CSW#TRLTC1421CSW-2.5
Manufacturer:
LT
Quantity:
44
APPLICATIONS
can usually be prevented by using logic that does not
include the clamping diodes such as the QSI 74FCTT
family from Quality Semiconductor, or by using a data bus
switch such as the 10-bit QS3384 QuickSwitch also from
Quality Semiconductor (Tel: 408-450-8000). The
QuickSwitch bus switch contains an N-channel placed in
series with the data bus. The switch is turned off when the
board is inserted and then enabled after the power is
stable. The switch inputs and outputs do not have a
parasitic diode back to V
The LTC1421 is designed to work directly with the
QuickSwitch bus switch as shown in Figure 13.
The DISABLE signal is connected to the enable pins of the
QS3384, and each switch is placed in series with a data
bus signal. When the board is inserted, the DISABLE
U
DISABLE
GATELO
PWRGD
GATEHI
V
V
RESET
FAULT
V
OUTLO
V
CON1
CON2
CPON
OUTHI
CCLO
CCHI
POR
CC
INFORMATION
U
and have very low capacitance.
1
W
2
3
20ms
Figure 14. Board Insertion Timing
U
4
5
V
TH1
signal is pulled high, turning off the switches. After the
board supply voltage ramps up and RESET goes high,
DISABLE will pull low enabling the switches.
Board Insertion Timing
When the board is inserted, GND pin makes contact first,
followed by V
DISABLE is immediately pulled high, so the data bus
switch is disabled. At the same time CON1 and CON2 make
contact and are shorted to ground on the host side (time
point 3). Since most boards need to be rocked back and
forth to get them in place, there is a period of time when
only one side of the connector is making contact. CON1
and CON2 should be located at opposite ends of the
connector.
200ms
6
CCHI
LTC1421/LTC1421-2.5
and V
CCLO
(Figure 14, time point 1).
1421 F14
13

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