LTC1421CSW#TR Linear Technology, LTC1421CSW#TR Datasheet - Page 9

• Manufacturer Part Number: LTC1421CSW#TR
• Description: IC CONTROLLER HOTSWAP ADJ 24SOIC
• Manufacturer: Linear Technology
• Type: Hot-Swap Controllerr

Specifications of LTC1421CSW#TR

• Applications: General Purpose
• Internal Switch(s): No
• Voltage - Supply: 3 V ~ 12 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 24-SOIC (0.300", 7.50mm Width)
• Linear Misc Type: Positive Low Voltage
• Family Name: LTC1421
• Package Type: SOIC W
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 12V
• Operating Temperature (min): 0C
• Operating Temperature (max): 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 24
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

APPLICATIONS
PWRGD and RESET
The LTC1421 uses a 1.232V bandgap reference, internal
resistive divider and a precision voltage comparator to
monitor V
The reset threshold voltage for V
the FB pin connection as summarized in Table 1.
Table 1
When the V
voltage, the comparator output goes low, and PWRGD is
immediately pulled high to V
current source or external resistor (Figure 7, time points
1 and 4). After a 200ms delay, RESET is pulled high. The
weak pull-up current source to V
RESET have a series diode so the pins can be pulled above
V
current back into V
PWRGD
V
PWRGD
RESET
RESET
OUTLO
CCLO
V2
by an external pull-up resistor without forcing
FEEDBACK PIN
1
V
OUTLO
CCLO
200ms
Floating
Figure 6. Supply Monitor Block Diagram
V
OUTLO
GND
OUTLO
Figure 7. Power Monitor Waveforms
20 A
32 s
(Figure 6).
TIMING
voltage rises above its reset threshold
RESET
V
CCLO
U
CCLO
2
20 A
.
V1
INFORMATION
U
V2
< 200ms
COMP1
3
CCLO
1.232V
V
OUTLO
OUTLO
V1
CCLO
W
by a weak pull-up
V2
–
+
RESET VOLTAGE
4
is determined by
4.65V
2.90V
5.88V
on PWRGD and
200ms
V
<32 s
OUTLO
73.5k
26.7k
71.5k
U
V2
5
V1
1421 F06
1421 F07
FB
REF
When V
parator output goes high, and PWRGD is immediately
pulled low (time point 2). After a 32 s delay, RESET is
pulled low. The RESET delay allows the PWRGD signal to
be used as an early warning that a reset is about to occur.
If the PWRGD signal is used as a interrupt input to a
microprocessor, a short power-down routine can be run
before the reset occurs.
If V
200ms, the PWRGD output will trip, but the RESET output is
not affected (time point 3). If V
threshold for less than 32 s, the PWRGD output will trip, but
again the RESET output will not be affected (time point 5).
Voltage Comparator
The uncommitted voltage comparator (COMP2) can be
used to monitor output voltages other than V
8a shows how the comparator can be used to monitor a
12V supply (V
ates a reset when it dips below 4.65V. When the 12V
supply drops below 10.8V, COMPOUT will pull low. The FB
pin is left floating.
Figure 8b shows how the comparator can be used to
monitor the 5V supply (V
(V
the 5V supply drops below 4.65V, COMPOUT will pull low.
The FB pin is tied to V
6
7
OUTLO
OUTLO
V
CCLO
V
20 A
OUTLO
) generates a reset when it dips below 2.9V. When
CCLO
Figure 8a. Monitor 12V, Reset 5V at 4.65V
rises above the reset threshold for less than
20 A
TIMING
RESET
1.232V
OUTHI
drops below its reset threshold, the com-
LTC1421/LTC1421-2.5
COMP1
), while the 5V supply (V
OUTLO
–
+
OUTHI
.
OUTLO
COMP2
5V
20
) while the 3.3V supply
73.5k
26.7k
71.5k
drops below the reset
LTC1421
+
–
OUTLO
1421 F08a
16
11
15
13
14
8
OUTLO
10k
5%
) gener-
. Figure
12V
9
107k
107k
1%
1%
13.7k
1%