MC33982BPNA Freescale Semiconductor, MC33982BPNA Datasheet - Page 26

• Manufacturer Part Number: MC33982BPNA
• Description: IC SWITCH HI SIDE SINGLE 16-PQFN
• Manufacturer: Freescale Semiconductor
• Type: High Sider

Specifications of MC33982BPNA

• Input Type: SPI
• Number Of Outputs: 1
• On-state Resistance: 2 mOhm
• Voltage - Supply: 6 V ~ 27 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 16-PQFN, 16-PowerQFN
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Current - Output / Channel: -
• Current - Peak Output: -

Address 1110 — Under-voltage / Over-voltage Register
(UOVR)
over-voltage and/or under-voltage protection. By default ([0]),
both protections are active. When disabled, an under-voltage
or over-voltage condition fault will not be reported in bits D1
and D0 of the output fault register.
Address x111 — TEST
accessible with SPI during normal operation.
SERIAL OUTPUT COMMUNICATION (DEVICE
STATUS RETURN DATA)
loaded. Meanwhile, the data is clocked out MSB- (OD7-) first
as the new message data is clocked into the SI pin. The first
eight bits of data clocking out of the SO, and following a
transition, are dependant upon the previously written SPI
word.
be representative of the initial message bits clocked into the
SI pin since the
feature is useful for daisy chaining devices as well as
message verification.
Table 16. Serial Output Bit Map Descriptions
SERIAL OUTPUT BIT ASSIGNMENT
serial input message, as explained in the following
paragraphs.
addressed during the prior communication. The contents of
bits OD6 : OD0 depend upon the bits D2 : D0 from the most
recent STATR command SOA2 : SOA0.
26
33982
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
SOA3 SOA2 SOA1 SOA0
x = Don’t care.
The UOVR register can be used to disable or enable the
The TEST register is reserved for test and is not
When the
Any bits clocked out of the SO pin after the first eight will
The eight bits of serial output data depend on the previous
Bit OD7 reflects the state of the watchdog bit (D7)
x
x
x
x
x
0
1
0
1
x
Previous STATR
D7, D2, D1, D0
0
0
0
0
1
1
1
1
1
1
Table 16
CS
CS
pin is pulled low, the output status register is
0
0
1
1
0
0
0
1
1
1
pin first transitioned to a Logic [0]. This
summarizes the SO register content.
0
1
0
1
0
1
1
0
0
1
WDin
WDin
WDin
WDin
WDin
WDin
OD7
0
1
0
1
OD6
OTF
0
0
0
1
1
1
1
1
–
OCHF
OD5
0
1
1
0
0
0
1
1
–
CS
OCLF
OD4
1
0
1
0
1
1
0
0
–
Serial Output Returned Data
transition of Logic [0] to Logic [1]. If there is a valid message
length, the data is latched into the appropriate registers. A
valid message length is a multiple of eight bits. At this time,
the SO pin is tri-stated and the fault status register is now
able to accept new fault status information.
the STATR-selected register data at the time the
to a Logic [0] during SPI communication and / or for the period
of time since the last valid SPI communication, with the
following exceptions:
Previous Address SOA[2:0] = 000
the current state of the Fault register (FLTR)
Previous Address SOA[2:0] = 001
IN_SPI programmed bits, respectively.
A valid message length is determined following a
The output status register correctly reflects the status of
• The previous SPI communication was determined to be
• Battery transients below 6.0 V resulting in an under-
• The
If the previous three MSBs are 000, bits OD6 : OD0 reflect
The data in bits OD1 and OD0 contain CSNS
See
invalid. In this case, the status will be reported as
though the invalid SPI communication never occurred.
voltage shutdown of the outputs may result in incorrect
data loaded into the status register. The SO data
transmitted to the MCU during the first SPI
communication following an under-voltage V
condition should be ignored.
the WAKE pin is at Logic [0] may result in incorrect data
loaded into the status register. The SO data transmitted
to the MCU during the first SPI communication following
this condition should be ignored.
FSM_HS
Fast SR
OL_dis
SOCH
OD3
OLF
Table 1
0
0
0
0
RST
pin transition from a Logic [0] to Logic [1] while
CSNS high
SOCL2
CD_dis
WDTO
OSD2
IN Pin
1110
OD2
UVF
Analog Integrated Circuit Device Data
0
–
CSNS EN
Freescale Semiconductor
SOCL1
OCLT1
FSI Pin
UV_dis
OSD1
IN dis
WD1
OD1
OVF
–
(Table
CS
WAKE Pin
EN
SOCL0
OV_dis
PWR
FAULT
IN_SPI
OCLT0
OSD0
WD0
OD0
A/O
is pulled
17).
and
CS
–