IDT72T55248L6-7BB IDT, Integrated Device Technology Inc, IDT72T55248L6-7BB Datasheet - Page 22

• Manufacturer Part Number: IDT72T55248L6-7BB
• Description: IC CTRL QUADMUX FLOW 324-BGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT72T55248L6-7BB

• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72T55248L6-7BB

the instructional register to the offset read command (Hex Value = 0x0007). The
TDO of the JTAG port will output data in a similar fashion as the serial
programming described above.
size of the device selected. Each offset register requires different total number
of bits depending on input and output bus width configuration. This total must be
programmed into the device in order for all the flags to be programmed correctly.
To change values of one or more offset register, all of the registers must be
reprogrammed serially again.
TIMING MODES: IDT STANDARD vs FIRST WORD FALL THROUGH
(FWFT) MODE
of operation: IDT Standard mode or First Word Fall Through (FWFT) mode.
The selection of which mode will operate is determined during master reset, by
the state of the FWFT input.
be selected. This mode uses the Empty Flag (EF) to indicate whether or not there
are any words present in the Queue. It also uses the Full Flag (FF) to indicate
whether or not the Queue has any free space for writing. In IDT Standard mode,
every word read from the Queue, including the first, must be requested using
the Read Enable (REN) and RCLK.
selected. This mode uses Output Ready (OR) to indicate whether or not there
is valid data at the data outputs. It also uses Input Ready (IR) to indicate whether
or not the Queue has any free space for writing. In the FWFT mode, the first word
written to an empty Queue goes directly to output bus after three RCLK rising
edges, applying RCS = LOW is not necessary. However, subsequent words
must be accessed using the (RCS) and RCLK. Various signals, in both inputs
and outputs operate differently depending on which timing mode is in effect. The
timing mode selected affects all internal Queues equally.
IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with
Mux/Demux/Broadcast functions 8K x 40 x 4, 16K x 40 x 4 and 32K x 40 x 4
The number of bits required to load the offset registers is dependent on the
The IDT72T55248/72T55258/72T55268 support two different timing modes
During master reset, if the FWFT pin is LOW, then IDT Standard mode will
If the FWFT pin is HIGH during master reset, then FWFT mode will be
Serial Bits
IDT72T55248
IW/OW = x40
1 - 13
14 - 26
27 - 39
40 - 52
53 - 65
66 - 78
79 - 91
92 - 104
IDT72T55248
IW/OW = x20
or
IDT72T55258
IW/OW = x40
1 - 14
15 - 28
29 - 42
43 - 56
57 - 70
71 - 84
85 - 98
99 - 112
Figure 4. Offset Registers Serial Bit Sequence
IDT72T55248
IW/OW = x20
or IDT72T55258
IW/OW = x20
or IDT72T55268
IW/OW = x40
1 - 15
16 - 30
31 - 45
46 - 60
61 - 75
76 - 90
91 - 105
106 - 120
22
IDT STANDARD MODE
outlined in Table 3. To write data into the Queue, Write Enable (WEN) and WCS
must be LOW. Data presented to the DATA IN lines will be clocked into the Queue
on subsequent transitions of the Write Clock (WCLK). After the first write is
performed, the Empty Flag (EF) will go HIGH after three clock latency.
Subsequent writes will continue to fill up the Queue. The Programmable Almost-
Empty flag (PAE) will go HIGH after n + 1 words have been loaded into the
Queue, where n is the empty offset value. The default setting for these values
are listed in Table 3. This parameter is also user programmable as described
in the serial writing and reading of offset registers section.
will cause the Programmable Almost-Full flag (PAF) to go LOW. Again, if no
reads are performed, the PAF will go LOW after (8,192-m) writes for the
IDT72T55248, (16,384-m) writes for the IDT72T55258, and (32,768-m) writes
for the IDT72T55268. This is assuming the I/O bus width is configured to x40.
If the I/O is x20, then PAF will go LOW after (16,384-m) writes for the
IDT72T55248, (32,768-m) writes for the IDT72T55258, and (65,536-m) writes
for the IDT72T55268. If the I/O is x10, then PAF will go LOW after (32,768-m)
writes for the IDT72T55248, (65,536-m) writes for the IDT72T55258, and
(131,072-m) writes for the IDT72T55268. The offset “m” is the full offset value.
The default setting for these values are listed in Table 3. This parameter is also
user programmable. See the section on serial writing and reading of offset
registers for details.
operations. If no reads are performed after a reset, FF will go LOW after D writes
to the Queue. If the I/O bus width is configured to x40, then D = 8,192 writes for
the IDT72T55248, 16,384 writes for the IDT72T55258, and 32,768 writes for
the IDT72T55268. If the I/O is x20, then D = 16,384 writes for the IDT72T55248,
32,768 writes for the IDT72T55258, and 65,536 writes for the IDT72T55268.
If the I/O is x10, then D = 32,768 writes for the IDT72T55248, 65,536 writes
for the IDT72T55258, and 131,072 writes for the IDT72T55268.
In this mode, the status flags FF, PAF, PAE, and EF operate in the manner
Continuing to write data into the Queue without performing read operations
When the Queue is full, the Full Flag (FF) will go LOW, inhibiting further write
IDT72T55258
IW/OW = x10
or
IDT72T55268
IW/OW = x20
1 - 16
17 - 32
33 - 48
49 - 64
65 - 80
81 - 96
97 - 112
113 - 128
IDT72T55268
IW/OW = x10
COMMERCIAL AND INDUSTRIAL
1 - 17
18 - 34
35 - 51
52 - 68
69 - 85
86 - 102
103 - 119
120 - 136
TEMPERATURE RANGES
FEBRUARY 01, 2009
Offset
Register
PAE3
PAF3
PAE2
PAF2
PAE1
PAF1
PAE0
PAF0
6157 drwAB