IDT72T55248L6-7BB IDT, Integrated Device Technology Inc, IDT72T55248L6-7BB Datasheet - Page 35

• Manufacturer Part Number: IDT72T55248L6-7BB
• Description: IC CTRL QUADMUX FLOW 324-BGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT72T55248L6-7BB

• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72T55248L6-7BB

Q
ECHO READ CLOCK (ERCLK0/1/2/3)
corresponding to their respective input read clocks in the Queue. The echo
read clock is a free-running clock output, that will always follow the RCLK input
regardless of the read enables and read chip selects. The ERCLK output
follows the RCLK input with an associated delay. This delay provides the user
with a more effective read clock source when reading data from the output bus.
This is especially helpful at high speeds when variables within the device may
cause changes in the data access times. These variations in access time may
be caused by ambient temperature, supply voltage, or device characteristics.
effect on the echo read clock output produced by the device, therefore the echo
read clock output level transitions should always be at the same position in time
relative to the data outputs. Note, that echo read clock is guaranteed by design
to be slower than the slowest data outputs. Refer to Figure 6, Echo Read Clock
and Data Output Relationship, Figure 27, Echo Read Clock and Read Enable
NOTES:
1. REN is LOW. OE is LOW.
2. t
3. Qslowest is the data output with the slowest access time, t
4. Time, t
5. DDR mode clocks data on rising and falling edge of RCLK.
IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with
Mux/Demux/Broadcast functions 8K x 40 x 4, 16K x 40 x 4 and 32K x 40 x 4
SLOWEST
There are four echo read clock outputs available in this device, each
Any variations effecting the data access time will also have a corresponding
ERCLK
ERCLK
RCLK
Figure 6. Echo Read Clock and Data Output Relationship
(3)
> t
D
is greater than zero, guaranteed by design.
A
, guaranteed by design.
t
A
t
ERCLK
t
D
t
A
(5)
A
.
6157 drw12
35
Operation in Double Data Rate Mode and Figure 28, Echo RCLK and Echo
REN Operation for timing information. The four echo read clock outputs operate
independent of one another and are direct copies of their respective RCLK
inputs.
ECHO READ ENABLE (EREN0/1/2/3)
corresponding to the individual Queues in memory. The echo read enable
output is provided to be used in conjunction with the echo read clock and
provides the device receiving data from the Queue with a more effective
scheme for reading the Queues’ data. The echo read enable output is
controlled by internal logic that becomes active for the read clock cycle that a
new word is read out of the Queue. That is, a rising edge of read clock will cause
echo read enable to go LOW, if both read enable and read chip select are active
and the Queue is not empty. In other words, every cycle puts data on the output
bus and drives EREN output to the LOW.
There are four echo read enable outputs available in this device, each
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
FEBRUARY 01, 2009