IDT72T55248L6-7BB IDT, Integrated Device Technology Inc, IDT72T55248L6-7BB Datasheet - Page 33

• Manufacturer Part Number: IDT72T55248L6-7BB
• Description: IC CTRL QUADMUX FLOW 324-BGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT72T55248L6-7BB

• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72T55248L6-7BB

(FWFT/SI) and serial clock (SCLK) when programming the offset registers.
When the serial write enable is LOW, data at the serial input is loaded into the
offset register, one bit for each LOW-to-HIGH transition of SCLK. When serial
write enable is HIGH, the offset registers retain the previous settings and no
offsets are loaded. Serial write enable functions the same way in both IDT
Standard and FWFT modes.
SERIAL READ ENABLE (SREN)
programmable offset registers. It is used in conjunction with the serial data output
(SDO) and serial clock (SCLK) when reading the offset registers. When the
serial read enable is LOW, data at the serial data output can be read from the
offset register, one bit for each LOW-to-HIGH transition of SCLK. When serial
read enable is HIGH, the reading of the offset registers will stop. Whenever serial
read enable (SREN) is activated values in the offset registers are read starting
from the first location in the offset registers. The SREN HIGH to LOW transition
copies the values in the offset registers directly into a serial scan out register.
SREN must be kept LOW in order to read the entire contents of the offset register.
If at any point SREN is toggled HIGH to LOW, another copy function from the
offset register to the serial scan out register will occur. Serial read enable
functions the same way in both IDT Standard and FWFT modes.
OUTPUTS:
DATA OUTPUT BUS (Q[39:0])
data outputs for the 40-bit wide data bus, Q[19:0] are data outputs for 20-bit wide
data bus, and Q[9:0] are data outputs for the 10-bit wide data bus. In Demux
and Broadcast mode the output bus will be 10 bits wide for each of the four internal
Queues. Q[9:0] are dedicated to Queue 0, Q[19:10] are dedicated to Queue
1, Q[29:20] are dedicated to Queue 2, and Q[39:30] are dedicated to Queue
3. In FWFT mode, when switching from one Queue to another, the data of the
newly selected Queue will always be present on the output bus two cycles after
the next RCLK cycle after OS[1:0] is selected providing RCS is LOW regardless
of whether or not REN is active. Thus each of the four Queues can be accessed
on every RCLK cycle.
EMPTY/OUTPUT READY FLAG (EF/OR0/1/2/3)
corresponding to the individual Queues in memory. This is a dual-purpose pin
that is determined based on the state of the FWFT/SI pin during master reset
for selecting one of the two timing modes of this device. In the IDT Standard mode,
the empty flags are selected. When an individual Queue is empty, its empty flag
will go LOW, inhibiting further read operations from that Queue. When the empty
flag is HIGH, the individual Queue is not empty and valid read operations can
be applied. See Figure 24, 25, Read Cycle, Empty Flag and First Word Latency
Timing (IDT Standard Mode), for the relevant timing information. Also see Table
3 “Status Flags for IDT Standard Mode” for the truth table of the empty flags.
go LOW at the same time that the first word written to an empty Queue appears
on the outputs, which is a minimum of three read clock cycles provided the RCLK
and WCLK meets the t
to-HIGH transitions that shifts the last word from the Queue to the outputs. OR
goes HIGH when an enabled read operation is performed to an empty queue.
The previous data stays at the outputs, indicating the last word was read. Further
data reads are inhibited until a new word is on the bus when OR goes LOW again.
See Figure 21, 22, 23, Read Timing (FWFT Mode), for the relevant timing
information. Also see Table 4 “Status Flags for FWFT Mode” for the truth table
of the empty flags.
IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with
Mux/Demux/Broadcast functions 8K x 40 x 4, 16K x 40 x 4 and 32K x 40 x 4
The serial read enable input is an enable used for reading the value of the
The data output bus can be 40, 20, or 10 bits wide in Mux mode. Q[39:0] are
There are four empty/output ready flags available in this device, each
In FWFT mode, the output ready flags are selected. Output ready flags (OR)
SKEW
parameter. OR stays LOW after the RCLK LOW-
33
edge of RCLK. In IDT Standard mode, the flags are double register-buffered
outputs. In FWFT mode, the flags are triple register-buffered outputs. The four
empty flags operate independent of one another and always indicate the
respective Queue’s status.
COMPOSITE EMPTY/OUTPUT READY FLAG (CEF/COR)
selected. The composite empty/output ready flag represents the state of the
Queue selected on the read port, such that the user does not have to monitor
each individual Queues’ empty/output ready flags. The composite empty/output
ready flag is only available in Mux mode, since the output select bits (OS[1:0])
are used to select any one of the four Queues to read from.
and FWFT modes. In IDT Standard mode, when switching from one Queue to
another, the composite empty flag will update to the status of the newly selected
Queue one RCLK cycle after the rising edge of RCLK that made the new Queue
selection. In FWFT mode, the composite output ready flag will update to the status
of the newly selected Queue on two clock cycles after the rising edge of RCLK
that made the new Queue selection. See Figures 26, 27 for the associated timing
diagram. See Table 3 and 4 “Status Flags for IDT Standard and FWFT Mode
“ for the truth table of the composite empty flag.
FULL/INPUT READY FLAG (FF/IR0/1/2/3)
to the individual Queues in memory. This is a dual-purpose pin that is determined
based on the state of the FWFT/SI pin during master reset for selecting the two
timing modes of this device. In the IDT Standard mode, the full flags are selected.
When an individual Queue is full, its full flags will go LOW after the rising edge
of WCLK that wrote the last word, thus inhibiting further write operations to the
Queue. When the full flag is HIGH, the individual Queue is not full and valid write
operations can be applied. See Figures 14, 15, 16, Write Cycle, Full Flag and
First Word Latency Timing (IDT Standard Mode), for the associated timing
diagram. Also see Table 3 “Status Flags for IDT Standard Mode” for the truth
table of the full flags.
when there is adequate memory space in the Queues for writing in data. The
input ready flags go HIGH after the rising edge of WCLK that wrote the last word,
when there are no free spaces available for writing in data. See Figures 17,
18, 19, Write Timing (FWFT Mode), for the associated timing information. Also
see Table 4 “Status Flags for FWFT Mode” for the truth table of the full flags. The
input ready status not only measures the depth of the Queues memory, but also
counts the presence of a word in the output register. Thus, in FWFT mode, the
total number of writes necessary to make IR HIGH is one greater than needed
to set FF = LOW in IDT Standard mode.
all write operations to every Queue will be disabled. This maintains data integrity
throughout all four Queues for comparison. In all other modes, the full flag will
only disable write operations to its corresponding Queue.
double register-buffered outputs. The four full flags operate independent of one
another, except in Broadcast mode.
will go LOW with respect to WCLK, when the maximum number of words has
been written into the Queue, thus inhibiting further write operations. Upon the
completion of a valid read cycle, the full flag will go HIGH with respect to WCLK
two cycles later, thus allowing another write to occur, provided t
met.
The empty/output ready flags are synchronous and updated on the rising
This status pin is used to determine the empty state of the current Queue
The timing of the composite empty/output ready flag differs in IDT Standard
There are four full/input ready flags available in this device, each corresponding
In FWFT mode, the input ready flags are selected. Input ready flags go LOW
In Broadcast mode, when any one of the four full flags becomes asserted,
FF/IR is synchronous and updated on the rising edge of WCLK. FF/IR are
To prevent data overflow in the IDT Standard mode, the full flag of each Queue
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
FEBRUARY 01, 2009
SKEW
has been