IDT88P8342BHI IDT, Integrated Device Technology Inc, IDT88P8342BHI Datasheet - Page 17
IDT88P8342BHI
Manufacturer Part Number
IDT88P8342BHI
Description
IC SPI3-SPI4 EXCHANGE 820-PBGA
Manufacturer
IDT, Integrated Device Technology Inc
Datasheet
1.IDT88P8342BHGI.pdf
(98 pages)
Specifications of IDT88P8342BHI
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
88P8342BHI
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3.2 SPI-4
tation agreement.
3.2.1 SPI-4 ingress
IDT88P8342 SPI EXCHANGE 2 x SPI-3 TO SPI-4
Refer to OIF SPI-4 document (see Glossary) for full details of the implemen-
- Clock rate is 80 - 400 MHz (160 - 800MHz DDR)
- Link and PHY modes supported
- Address range 0 to 255 with support for 128 simultaneously active logical
- MAXBURST parameters configurable 16-256 bytes in 16 byte multiples
- 256 entry calendar
- LVTTL and LVDS status signals supported
The following are implemented for the SPI-4 interface:
- Link / PHY layer device
- Physical port active
The SPI-4 ingress includes
•
•
•
•
•
ports
Bit alignment
Word alignment/ de-skew
Transfer decode and dispatch
PFP interface
Status frame generation
17
SPI-4 ingress configurable parameters
SPI-4 LID map
Word / bit synchronization
Minimum packet length
short packet counter.
Maximum packet length
long packet counter.
Free segment backpressure threshold
- 256 entries, one per SPI-4 LP
- SPI-3 physical interface identifier
- Physical port enable
- LVDS clock data alignment and LVDS data de-skew
- Packets shorter than the minimum length will be optionally counted in the
- Range 0 – 255 in 1 byte increments
- Packets longer than the maximum length will be optionally counted in the
- Range 0 – 16,383 in 1 byte increments
- Number of free buffer segments allocated to trigger backpressure for the LP
INDUSTRIAL TEMPERATURE RANGE
APRIL 10, 2006
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