IDT88P8342BHI IDT, Integrated Device Technology Inc, IDT88P8342BHI Datasheet - Page 53

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IDT88P8342BHI

Manufacturer Part Number
IDT88P8342BHI
Description
IC SPI3-SPI4 EXCHANGE 820-PBGA
Manufacturer
IDT, Integrated Device Technology Inc
Datasheet

Specifications of IDT88P8342BHI

Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
88P8342BHI
rupt indication enable.
to an unavailable condition interrupt indication enable.
on the SPI-4 egress status channel.
synchronization to in synchronization condition interrupt indication enable.
to an unavailable condition interrupt indication enable. SCLK_UN_EN should
be written as a zero if using a SPI-4 egress LVTTL status clock that is less than
one-half of the MCLK frequency. The SCLK_UN_I interrupt indication is not
usable in this case.
Module status register (0x24 and 0x25 in the direct
accessed space)
TABLE 42 - MODULE STATUS REGISTER (0x24
AND 0x25 IN THE DIRECT ACCESSED SPACE)
have read and write access, and interrupt status fields are cleared by a
microprocessor write cycle, where a logical one must be written to clear the
field(s) targeted, except for the PMON field, which can not be cleared.
only be active if the corresponding field is active in the Primary Interrupt Status
Register (Direct 0x2C):
MODULE_A field is active in the Primary Interrupt Status Register.
MODULE_B field is active in the Primary Interrupt Status Register.
IDT88P8342 SPI EXCHANGE 2 x SPI-3 TO SPI-4
SPI-34_CAPTURE
SPI-43_CAPTURE
SPI-34_INSERT
SPI-43_INSERT
PMON
Reserved
I_BUS_ERR_EN
0=Disable bus error interrupt
1=Enable bus error interrupt
SPI4_INACTIVE_TRANSFER_EN SPI-4 ingress inactive transfer inter-
0=Disable inactive transfer interrupt
1=Enable inactive transfer interrupt
DCLK_UN_EN SPI-4 ingress data clock has transitioned from available
0=Disable unavailable interrupt
1=Enable unavailable interrupt
E_DIP_ERR_EN
0=Disable DIP-2 error interrupt
1=Enable DIP-2 error interrupt
E_SYNCH_EN SPI-4 egress status channel has transitioned from out of
0=Disable synchronization interrupt
1=Enable synchronization interrupt
SCLK_UN_EN SPI-4 egress status clock has transitioned from available
0=Disable unavailable interrupt
1=Enable unavailable interrupt
The Module Status registers (0x24 and 0x25 in the direct accessed space)
The Module Status registers are secondary interrupt status registers and can
Module Status Register 0x24 is for module A, and can only be active if the
Module Status Register 0x25 is for module B, and can only be active if the
Field
SPI-4 egress DIP-2 error interrupt indication enable
SPI-4 ingress bus error interrupt indication enable.
Bits
7:5
0
1
2
3
4
Length
1
1
1
1
1
3
Initial Value
0
0
0
0
0
0
53
rupt indication.
indication.
indication.
indication.
no effect.
Module enable register (0x28 and 0x29 in the
direct accessed space)
TABLE 43 - MODULE ENABLE REGISTER (0x28
AND 0x29 IN THE DIRECT ACCESSED SPACE)
have read and write access.
interrupt enable.
interrupt enable.
enable.
SPI-34 CAPTURE_EN
SPI-43 CAPTURE_EN
SPI-34 INSERT_EN
SPI-43 INSERT_EN
PMON_EN
Reserved
SPI-34_CAPTURE
0=No capture event
1=Buffer is ready for reading by the microprocessor
SPI-43_CAPTURE SPI-4 ingress to SPI-3 egress capture event interrupt
0=No capture event
1=Buffer is ready for reading by the microprocessor
SPI-34_INSERT SPI-3 ingress to SPI-4 egress insert event interrupt
0=No insert event
1=Buffer is ready for writing by the microprocessor
SPI-43_INSERT
0=No insert event
1=Buffer is ready for writing by the microprocessor
PMON Performance Monitor event interrupt indication. Writing to this field has
0=No PMON event
1=PMON event is ready for reading by the microprocessor
The Module Enable registers (0x28 and 0x29 in the direct accessed space)
Module Enable Register 0x28 is for module A.
Module Enable Register 0x29 is for module B.
SPI-34_CAPTURE_EN
0=Disable capture interrupt
1=Enable capture interrupt
SPI-43_CAPTURE_EN
0=Disable capture interrupt
1=Enable capture interrupt
SPI-34_INSERT_EN SPI-3 ingress to SPI-4 egress insert event interrupt
0=Disable insert interrupt
1=Enable insert interrupt
Field
SPI-4 ingress to SPI-3 egress insert event interrupt
SPI-3 ingress to SPI-4 egress capture event inter-
SPI-3 ingress to SPI-4 egress capture event
SPI-4 ingress to SPI-3 egress capture event
INDUSTRIAL TEMPERATURE RANGE
Bits
7:5
0
1
2
3
4
Length
1
1
1
1
1
3
APRIL 10, 2006
Initial Value
0
0
0
0
0
0

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