IDT88P8342BHI IDT, Integrated Device Technology Inc, IDT88P8342BHI Datasheet - Page 34

• Manufacturer Part Number: IDT88P8342BHI
• Description: IC SPI3-SPI4 EXCHANGE 820-PBGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT88P8342BHI

• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 88P8342BHI

4.4 Microprocessor interface to SPI-3 datapath
capture/insert configurable parameters
is dependent on the egress control register). For each direction, the following
are to be used:
asserted by microprocessor for insertion.
SPI-3 and SPI-4.
Capture data fragment
microprocessor. The capture buffer can store only one 256 byte packet
fragment. When the buffer is full the DATA_AVAILABLE flag is set and a SPI-
3 capture event is generated. The event is directed towards the interrupt
module.
IDT88P8342 SPI EXCHANGE 2 x SPI-3 TO SPI-4
Enable insertion / capture of data to the SPI-3 or SPI-4 data stream (which
- Data for insertion or data captured
- Data available: set when data is available. Asserted by device for capture,
- LID: Logical Identifier of capture / insertion channel
- Length: length of data for insertion or capture
- Flags: SOP, EOP, address parity error, data parity error, packet error
There are separate instantiations of microprocessor insert capture buffers for
Packets can be captured from the SPI-3-4 stream and directed towards the
Min: 19.44MHz
Max: 133MHz
8 bit / 32 bit
4 x SPI-3
Figure 23. SPI-3 ingress to microprocessor capture interface datapath
t+1
t
t+258
Figure 22 . Microprocessor data capture buffer
SOP
7
JTAG
LID Counters Memory
data[255]
data[2]
data[1]
data[0]
length
flags
lid
uproc
Memory
SPI-3 /
LID map
EA
Main
A
ED
34
PAR EOP
Read packet data fragment
verifies the DATA_AVAILABLE flag in the SPI-3 capture control register.
Microprocessor reads the packet fragment and EOP, SOP, ERROR, LID and
LENGTH fields from the SPI-3 data capture buffer. Microprocessor hands over
control of the capture buffer when it clears the DATA_AVAILABLE flag in the SPI-
3 data capture control register (Table 31 - SPI-3 data capture control register).
4.4.1 SPI-3 to ingress microprocessor interface
datapath
interface to the microprocessor capture interface.
the device.
except the last fragment of a packet which may be shorter. The LP address is
in-band with the data. The fragment enters a SPI-3 ingress buffer. SPI-3 LP
address, error information, SOP, and EOP are stored with the fragment. The LP
address is mapped to a LID. The fragment is stored in LID allocated buffer segments.
and the PFP decides to send this LID to the microprocessor capture port. Data
is moved to the capture buffer along with the LP address. LID, error information,
SOP, and EOP. The data available bit is set. Data and control information are
read from the relevant register space through the microprocessor interface.
Chip Counters Memory
The microprocessor needs to read a buffer to capture a packet fragment. It
The diagram below shows the datapath through the device from the SPI-3
The following is a description of the path taken by a fragment of data through
Data enters on a SPI-3 interface in fragments. Fragments are of equal length
The Table 80, SPI-3 egress port descriptor table (64 entries) is consulted,
0
t+1
t
t+258
SPI-4 /
LID map
EA
ED
PAR
6371 drw15
address parity error
data parity error
packet error
not used
Max: 400 MHz
Min: 80 MHz
6371 drw28
INDUSTRIAL TEMPERATURE RANGE
SPI-4.2
APRIL 10, 2006