IDT72P51777L7-5BBI IDT, Integrated Device Technology Inc, IDT72P51777L7-5BBI Datasheet - Page 10

• Manufacturer Part Number: IDT72P51777L7-5BBI
• Description: IC FLOW CTRL 40BIT 376-BGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT72P51777L7-5BBI

• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72P51777L7-5BBI

PIN DESCRIPTIONS
IDT72P51767/72P51777 1.8V, MULTI-QUEUE FLOW-CONTROL DEVICES
(128 QUEUES) 40 BIT WIDE CONFIGURATION 5,898,240 and 11,796,480 bits
BM [3:0]
(BM3-BB13
BM2-AA12
BM1-BB12
BM0-BB11)
BOI
(P20)
D[39:0]
(See Pin No.
table for details)
DFM
(AA11)
EF
(N21)
ERCLK
(E22)
ERCLK
(F20)
EREN
(E21)
ESTR
(R20)
ESYNC
(P21)
EXI
(R21)
EXO
(P22)
FF
(E1)
Symbol &
(Pin No.)
Bus Matching
Back Off One
Mode
Data Input Bus
Default Mode
Empty Flag
Echo Read
Clock
Echo Read
Clock
Echo Read
Enable
PAEn Flag Bus
PAEn Bus Sync
PAEn Bus
Expansion In
PAEn Bus
Expansion Out
Full Flag
Name
1.8V LVTTL
1.8V LVTTL
I/O TYPE
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
HSTL
HSTL
HSTL
HSTL
HSTL
HSTL
HSTL
HSTL
HSTL
HSTL
HSTL
These pins define the bus width and data transfer rate (DDR/SDR) of the input write port and the output
read port of the device. The bus widths/data rates are set during a Master Rest cycle. The BM[3:0] signals
must meet the setup and hold time requirements of Master Reset and must not toggle/change state after
a Master Reset cycle.
When in BOI, data is back-off one position in which Packet 1 and Packet 2 are out again during second
Queue Switch. See section on 10Gbps Multi-queue Differences from the 4M multi-queue, previous page.
These are the 32 data input pins. Data is written into the device via these input pins on the rising edge
of WCLK provided that WEN is LOW. Any unused data input pins should be tied HIGH.
The 10G multi-queue device requires programming after master reset. The user can do this serially via
the serial port, or the user can use the default method. If DFM is LOW at Master Reset then serial mode
will be selected, if DFM is HIGH then default mode is selected.
The Empty Flag (EF) provides valid status for the selected queue. The Empty Flag indicates the selected
queue is empty, all words have been read. This flag is delayed to match the data output path delay.
The rising edge of this clock is centered aligned with Qout data.
Read Clock Echo is the inverse of ERCLK.
Echo Read Enable output, used in conjunction with ERCLK and ERCLK.
If direct operation of the PAEn bus has been selected, the ESTR input is used in conjunction with RCLK
and the RDADD bus to select a quadrant of queues to be placed on to PAEn output. A quadrant addressed
via the RDADD bus is selected on the rising edge of RCLK provided that ESTR is HIGH. If Polled operation
has been selected, ESTR should be tied inactive, LOW. Note, that a PAEn flag bus selection cannot be made,
(ESTR must NOT go active) until programming of the part has been completed and SENO has gone LOW.
ESYNC is an output from the multi-queue device that provides a synchronizing pulse for the PAEn bus
during Polled operation of the PAEn bus. During Polled operation each quadrant of queue status flags
is loaded on to the PAEn bus outputs sequentially based on RCLK. The first RCLK rising edge loads
quadrant 1 on to PAEn, the second RCLK rising edge loads quadrant 2 and so on. The fifth RCLK rising
edge will again load quadrant 1. During the RCLK cycle that quadrant 1 of a selected device is placed
on to the PAEn bus, the ESYNC output will be HIGH. For all other quadrants of that device, the ESYNC
output will be LOW.
The EXI input is used when multi-queue devices are connected in expansion mode and Polled PAEn bus
operation has been selected. EXI of device ‘N’ connects directly to EXO of device ‘N-1’. The EXI receives
a token from the previous device in a chain. In single device mode the EXI input must be tied LOW if the
PAEn bus is operated in direct mode. If the PAEn bus is operated in polled mode the EXI input must be
connected to the EXO output of the same device. In expansion mode the EXI of the first device should be
tied LOW, when direct mode is selected.
EXO is an output that is used when multi-queue devices are connected in expansion mode and Polled
PAEn bus operation has been selected. EXO of device ‘N’ connects directly to EXI of device ‘N+1’. This
pin pulses when device N has placed its final (4th) quadrant on to the PAEn bus with respect to RCLK.
This pulse (token) is then passed on to the next device in the chain ‘N+1’ and on the next RCLK rising
edge the first quadrant of device N+1 will be loaded on to the PAEn bus. This continues through the chain
and EXO of the last device is then looped back to EXI of the first device. The ESYNC output of each device
in the chain provides synchronization to the user of this looping event.
This pin provides the full flag output for the active Queue, that is, the queue selected on the input port for
write operations, (selected via WCLK, WRADD bus and WADEN). On the WCLK cycle after a queue
selection, this flag will show the status of the newly selected queue. Data can be written to this queue
provided FF is HIGH. This flag has High-Impedance capability, this is important during expansion of
D[39:36] user definable input bits
D[33] user definableD[32] user definableD[31:0] data input bits
10
Description
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
FEBRUARY 11, 2009