IDT72P51777L7-5BBI IDT, Integrated Device Technology Inc, IDT72P51777L7-5BBI Datasheet - Page 22

• Manufacturer Part Number: IDT72P51777L7-5BBI
• Description: IC FLOW CTRL 40BIT 376-BGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT72P51777L7-5BBI

• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72P51777L7-5BBI

FUNCTIONAL DESCRIPTION
MASTER RESET
to HIGH. During a master reset all internal multi-queue device setup and control
registers are initialized and require programming either serially by the user via
the serial port, or via parallel programming or by using the default settings. Refer
to Figure 6, Device Programming Hierarchy for the programming hierarchy
structure. During a master reset the state of the following inputs determine the
functionality of the part, these pins should be held HIGH or LOW.
TABLE 4 — DEVICE PROGRAMMING MODE COMPARISON
IDT72P51767/72P51777 1.8V, MULTI-QUEUE FLOW-CONTROL DEVICES
(128 QUEUES) 40 BIT WIDE CONFIGURATION 5,898,240 and 11,796,480 bits
Programming Options
Queue Selection
Queue Depth
PAE/PAF
Bus-Matching
I/O voltage
A Master Reset is performed by toggling the MRS input from HIGH to LOW
FM – Flag bus Mode
BM [3:0] – Bus Matching options
MAST – Master Device
ID0, 1, 2 – Device ID
QSEL[2:0] Queue Select Mode
QSEL[2:0]
DFM
MRS
See Table for definition of value
DFM = LOW for Serial Programming mode
Any number from 1 to 128
Each queue depth can be individualized
Programmable to any value
Any available option can be selected using
BM[3:0] pins
Any available option can be selected
Serial Programming Mode
Figure 4. Reference Signals
22
serially or via the default method before any read/write operations can begin.
PROGRAMMING MODE CAPTURED
captured. Once the programming mode signals are captured (latched), refer
to Table 5, Setting the Queue Programming Mode during Master Reset for
details. It will then require a number of clock cycles for the device to complete
the configuration. Configuration completion is indicated when the SENO signal
transitions from high to low. The configuration completion indication is consistent
with the previous MQ device.
DFM – Programming mode, serial or default
Once a master reset has taken place, the device must be programmed either
See Figure 37, Master Reset for relevant timing.
On the rising of MRS the programming mode signals (QSEL [2:0], DFM) are
Default/Parallel Programming Mode
Any number from 1 to 128
Default Value (total available memory divided
by number of queues)
Default value
Any available option can be selected using
BM[3:0] pins
Any available option can be selected
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
FEBRUARY 11, 2009
6724 drw06