IDT72P51777L7-5BBI IDT, Integrated Device Technology Inc, IDT72P51777L7-5BBI Datasheet - Page 54

• Manufacturer Part Number: IDT72P51777L7-5BBI
• Description: IC FLOW CTRL 40BIT 376-BGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT72P51777L7-5BBI

• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72P51777L7-5BBI

‘x’, then there may be an extra WCLK cycle delay before that queues status is
correctly shown on the respective output of the PAFn bus. However, the active
PAF flag will show correct status at all times.
word on the PAFn bus can change every WCLK cycle. Also, data present on
the input bus, Din, can be written into a Queue on the same WCLK rising edge
that a status word is being selected, the only restriction being that a write queue
selection and PAFn status word selection cannot be made on the same cycle.
output on PAF[0:7] constantly.
device the PAFn busses of all devices are connected together, when switching
between status words of different devices the user must utilize the 1-3 most
significant bits of the WRADD address bus (as well as the 2 LSB’s). These 1-
3 MSb’s correspond to the device ID inputs, which are the static inputs, ID0, ID1
& ID2.
timing information. Also refer to Table 8, Write Address Bus, WRADD.
PAFn – POLLED BUS
mode. In polled mode the PAFn bus only cycles through the number of status
words required to display the status of the number of queues that have been
setup in the part. Every rising edge of the WCLK causes the next status word
to be loaded on the PAFn bus. The device configured as the master (MAST
input tied HIGH), will take control of the PAFn after MRS goes LOW. For the whole
WCLK cycle that the first status word is on PAFn the FSYNC (PAFn bus sync)
output will be HIGH, for all other status words, this FSYNC output will be LOW.
This FSYNC output provides the user with a mark with which they can
synchronize to the PAFn bus, FSYNC is always HIGH for the WCLK cycle that
the first status word of a device is present on the PAFn bus.
will be set as the Master (ID = '000'), MAST input tied HIGH, all other devices
will have MAST tied LOW. The master device is the first device to take control
of the PAFn bus and will place its first status word on the bus on the rising edge
of WCLK. For the next n WCLK cycles (n= number of queues divided by 8 with
n being increased by one for any remainder) the master device will maintain
control of the PAFn bus and cycle its status words through it, all other devices
hold their PAFn outputs in High-Impedance. When the master device has cycled
all of its status words it passes a token to the next device in the chain and that
device assumes control of the PAFn bus and then cycles its status words and
so on, the PAFn bus control token being passed on from device to device. This
token passing is done via the FXO outputs and FXI inputs of the devices (“PAF
Expansion Out” and “PAF Expansion In”). The FXO output of the master device
connects to the FXI of the second device in the chain and the FXO of the second
connects to the FXI of the third and so on. The final device in a chain has its FXO
connected to the FXI of the first device, so that once the PAFn bus has cycled
through all status words of all devices, control of the PAFn will pass to the master
device again and so on. The FSYNC of each respective device will operate
independently and simply indicate when that respective device has taken control
of the bus and is placing its first status word on to the PAFn bus.
the FXO output of the same device. In single device mode a token is still required
to be passed into the device for accessing the PAFn bus.
IDT72P51767/72P51777 1.8V, MULTI-QUEUE FLOW-CONTROL DEVICES
(128 QUEUES) 40 BIT WIDE CONFIGURATION 5,898,240 and 11,796,480 bits
Status words can be selected on consecutive clock cycles, that is the status
If 8 or less queues are setup then queues, Queue[0:7] have their PAF status
When the multi-queue devices are connected in expansion of more than one
Please refer to Figure 57 PAFn - Direct Mode Status Word Selection for
If FM is HIGH at master reset then the PAFn bus operates in Polled (looped)
When devices are connected in expansion configuration, only one device
When operating in single device mode the FXI input must be connected to
Please refer to Figure 60, PAFn Bus – Polled Mode for timing information.
54
PAEn FLAG BUS OPERATION
configured for up to 128 queues, each queue having its own almost empty/
packet ready status. An active queue has its flag status output to the discrete flag,
PAE, on the read port. Queues that are not selected for a read operation can
have their PAE status monitored via the PAEn bus. The PAEn flag bus is 8 bits
wide, so that 8 queues at a time can have their status output to the bus. If 9 or
more queues are setup within a device then there are 2 methods by which the
device can share the bus between queues, "Direct" mode and "Polled" mode
depending on the state of the FM (Flag Mode) input during a Master Reset. If
8 or less queues are setup within a device then each will have its own dedicated
output from the bus. If 8 or less queues are setup in single device mode, it is
recommended to configure the PAFn bus to polled mode as it does not require
using the write address (WRADD).
PAEn - DIRECT BUS
mode. In direct mode the user can address the status word of queues they
require to be placed on to the PAEn bus. For example, consider the operation
of the PAEn bus when 26 queues have been setup. To output status of the first
status word, Queue[0:7] the RDADD bus is used in conjunction with the ESTR
(PAE flag strobe) input and RCLK. The address present on the 2 least significant
bits of the RDADD bus with ESTR HIGH will be selected as the status word
address on a rising edge of RCLK. So to address status word 1, Queue[0:7]
the RDADD bus should be loaded with “xxxx0000”, the PAEn bus will change
status to show the new status word selected 1 RCLK cycle after status word
selection. PAEn[0:7] gets status of queues, Queue[0:7] respectively.
“xxxx0001”. PAEn[0:7] gets status of queues, Queue[8:15] respectively. To
address the third status word, Queue[16:23], the RDADD address is “xxxx0010”.
PAE[0:7] gets status of queues, Queue[16:23] respectively. To address the
fourth status word, Queue[24:31], the RDADD address is “xxxx0011”.
PAE[0:1] gets status of queues, Queue[24:25] respectively. Remember, only
26 queues were setup, so when status word 4 is selected the unused outputs
PAE[2:7] will be don't care states.
queue ‘x’ on the same cycle as a status word switch which will include the queue
‘x’, then there may be an extra RCLK cycle delay before that queues status is
correctly shown on the respective output of the PAEn bus.
word on the PAEn bus can change every RCLK cycle. Also, data can be read
out of a Queue on the same RCLK rising edge that a status word is being selected,
the only restriction being that a read queue selection and PAEn status word
selection cannot be made on the same RCLK cycle.
output on PAE[0:7] constantly.
device the PAEn busses of all devices are connected together, when switching
between status words of different devices the user must utilize the 3 most
significant bits of the RDADD address bus (as well as the 2 LSB’s). These 3
MSb’s correspond to the device ID inputs, which are the static inputs, ID0, ID1
& ID2.
timing information. Also refer to Table 9, Read Address Bus, RDADD.
The IDT72P51767/72P51777 multi-queue flow-control device can be
If FM is LOW at master reset then the PAEn bus operates in Direct (addressed)
To address the second status word, Queue[8:15], the RDADD address is
Note, that if a read or write operation is occurring to a specific queue, say
Status words can be selected on consecutive clock cycles, that is the status
If 8 or less queues are setup then queues, Queue[0:7] have their PAE status
When the multi-queue devices are connected in expansion of more than one
Please refer to Figure 56, PAEn - Direct Mode Status Word Selection for
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
FEBRUARY 11, 2009