IDT89TTM552BL IDT, Integrated Device Technology Inc, IDT89TTM552BL Datasheet

no-image

IDT89TTM552BL

Manufacturer Part Number
IDT89TTM552BL
Description
IC TRAFFIC MANAGER 1192-FCBGA
Manufacturer
IDT, Integrated Device Technology Inc
Datasheet

Specifications of IDT89TTM552BL

Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
89TTM552BL

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
IDT89TTM552BL
Manufacturer:
IDT
Quantity:
2
Description
engines and one or more crossbar/schedulers. The main function of the
89TSF5xx is to route traffic from the source to the destination in a fair
and efficient way. It can be configured in many ways that achieve fair-
ness, balance loads, minimize traffic congestion, and protect against
failure. These devices interconnect using sets of high-speed SerDes
links. They are scalable, and bandwidth increases linearly when you add
multiple 89TSF500s. A functional block diagram of the 89TSF500 is
shown in Figure 1.
a line card
“switch” of the 89TSF5xx switch fabric. Combined, they provide up to
10 Gbps switching bandwidth per system port and up to 32 system ports
or 64 system subports
serial links. The 89TSF5xx system can be implemented on a single shelf
or on multiple shelves. Figure 2 is an example of a single-shelf system,
while Figures 3 and 4 illustrate multiple-shelf systems.
that gives system designers maximum flexibility and performance. This
architecture allows a switch to be implemented either on a single shelf
using an electrical backplane or on multiple shelves connected by
optical transceivers, thus helping system vendors overcome physical
space constraints.
has a non-blocking architecture and supports up to 8 classes of service
and spatial multicasting. It performs data switching and circuit switching
concurrently, providing guaranteed bandwidth and fixed jitter for the
circuit paths.
duplex, providing the benefits of high density, low cost, and low power.
Multiple 89TSF500s can be combined to support system configurations
up to 32 line cards at 10 Gbps, full duplex.
89TSF5xx Features
© 2004 Integrated Device Technology, Inc.
The 89TSF5xx is a complete switch fabric, consisting of two chips:
The 89TSF5xx switch fabric is a system of one or more queueing
The 89TSF552 is the interface of a system port (usually equivalent to
The 89TSF5xx switch fabric devices interconnect using high speed,
The 89TSF5xx switch fabric has a modular and scalable architecture
The 89TSF500 consists of an integrated crossbar and a scheduler. It
A single 89TSF500 has an aggregate bandwidth of 64 Gbps, full
1.
card would be equivalent to a system port. However, a 20 Gbps line card would
have two 89TSF552s and therefore that line card is equivalent to 2 system
ports.
2.
Up to 32 switch ports, with 24 Gbps available per switch port.
A 10 Gbps line card would have a single 89TSF552 and therefore that line
One 89TSF552 can support up to 4 system subports.
89TSF552 (queuing engine, 10 Gbps).
89TSF500 (crossbar and scheduler).
1
) to the 89TSF5xx switch fabric. The 89TSF500 is the
2
per system.
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.
Switch Fabric Data Sheet
*Notice: The information in this document is subject to change without notice
1 of 37
89TSF500 Features
– A maximum of 32 ports with 8 CoS, or
– A maximum of 16 ports with 4 subports and 4 CoS.
– Flexible architecture that allows the 89TSF switch fabric to be
– Automatic link diagnostics that detect faulty link connections.
– Both n+m (load-sharing mode) and 1:1 protection (active/
– Patented error correction scheme to reduce the system bit error
– Line cord redundancy via Redundant Destination Mapping
– Dynamic 89TSF500 rerouting that avoids congested or faulty
– Zero cell loss during controlled switchover to standby
Variable length CSIX payload (up to 132 bytes) that supports
any type of traffic.
Virtual output queues (VOQs) in the ingress direction that
eliminate head-of-line blocking. The 256 unicast VOQs
provide:
Spatial multicast support with up to 4K global multicast
labels. Each multicast label can specify from 1 to 32 ports.
Efficient backpressure mechanism that eliminates cell loss
caused by congestion.
In-service scalable architecture.
“Stackable” architecture. Total aggregate bandwidth is
linearly proportional to the number of 89TSF500s. Port rate is
configurable up to OC-192.
Always non-blocking architecture across destination, traffic
type (cell, packet), and class of service (CoS).
Supports up to 4 egress subports per switch port.
Carrier class reliability features:
Advanced diagnostic features including multiple loopback
paths.
Unicast and multicast traffic with up to 8 classes of service.
Industry-standard CSIX-over-LVDS interface.
Backward compatibility with IDT’s ZSF200 switch fabric.
32 embedded SerDes links per device at 2.5 Gbps per link.
Linear scalability for higher aggregate port density.
Combined unicast and multicast scheduling.
Clock synchronization and cell alignment across the fabric.
External processor interface for register config. and status.
employed in a single switch shelf or in multiple switch shelves.
standby mode) on serial links.
rate by 10
(RDM) and Queue-Mapped Redundancy (QMR).
89TSF500s.
89TSF500s.
5
.
Preliminary Information*
November 23, 2004
89TSF500
DSC 6798

Related parts for IDT89TTM552BL

IDT89TTM552BL Summary of contents

Page 1

Description The 89TSF5xx is a complete switch fabric, consisting of two chips: 89TSF552 (queuing engine, 10 Gbps). 89TSF500 (crossbar and scheduler). The 89TSF5xx switch fabric is a system of one or more queueing engines and one or more crossbar/schedulers. The ...

Page 2

IDT 89TSF500 Multicast Mask Traffic from SerDes ingress Rx 89TSF552s Line Card(s) Grant RAM (MMR) Scheduler Request Label (GS) Control (RLC) back request pressure labels ZCell Align Switch Input (AS) (ZI) 64 × 64 “ZAZ” CPU Interface (CPIF) Figure 1 ...

Page 3

IDT 89TSF500 Line Card(s) optical cables Line Card(s) optical cables Line Card CSIX 89TSF552 Functions optical interface Optical Interface Card(s) optical interface Optical Interface Card(s) 89TSF500 Switch Card(s) Figure 3 Multiple-Shelf System with Single Switch Shelf Line Card CSIX 89TSF552 ...

Page 4

IDT 89TSF500 89TTSF500 Pin Description Note: Information in this section is subject to change. Contact your IDT FAE before making design decisions. In this data sheet, direction is indicated as follows: I for In, O for Out, B for Bidirectional, ...

Page 5

IDT 89TSF500 Signal Name I/O Type RXN[31:0] Serdes diff input RXP[31:0] Serdes diff input TXN[31:0] Serdes diff input Serdes diff input TXP[31:0] VDD_SD VDD_TX Signal Name ZBUS_AVALID_N (pin AT5) 3.3V LVTTL ZBUS_CLK (pin AV3) 3.3V LVTTL ZBUS_AD[15:0] 3.3V LVTTL ZBUS_DEVID[4:0] ...

Page 6

IDT 89TSF500 Signal Name ZTICK (pin V4) ZTICK_MODE (pin V2) Signal Name RESET_N (pin AR3) CHN_DET_MODE (pin AU2) VDD VDD_IO VSS 89TSF500 Electrical Specifications Some data are TBD and will be published as they become available. The specifications are subject ...

Page 7

IDT 89TSF500 Symbol T Soldering temperature for green package GP_SOLDER T Rework temperature for green package GP_REWORK V I/O terminal voltage IO 89TSF500 Operating Ranges Symbol T Operating junction temperature range J V Core digital 1.8V power supply VDD V ...

Page 8

IDT 89TSF500 Symbol Parameter I Input current for core digital 1.8V VDD power supply I , Input current for PLL digital 1.8V PLL_SYS_VDD I power supply PLL_CORE_VDD I , Input current for PLL analog 3.3V PLL_SYS_VDDA I power supply PLL_CORE_VDDA ...

Page 9

IDT 89TSF500 89TSF500 AC Characteristics Unless otherwise stated, the following parameters are provided given the conditions outlined in Table 8. Symbol f System clock frequency (125 MHz ±0.1MHz) SYS T Jitter requirements (peak to peak) for system clock. Peak to ...

Page 10

IDT 89TSF500 T KQVZB ZBUS_CLK ZBUS_AD[15:0] ZBUS_DVALID_N ZBUS_PRTY ZBUS_INT_N[2:0] ZBUS_CLK T HZB ZBUS_AD[15:0] ZBUS_DVALID_N ZBUS_PRTY ZBUS_AVALID_N Symbol T Input setup time from system clock (SYS_CLK pin) rising edge SZT T Input hold time from system clock rising edge HZT T ...

Page 11

IDT 89TSF500 Symbol Parameter Common mode range V “Eye” opening PP (differential) f SerDes reference clock frequency SDREF D Percentage duty cycle for SerDes reference clock SDREF J Random jitter for SerDes reference clock SDREF fo Frequency offset between source ...

Page 12

IDT 89TSF500 Symbol Parameter Z Differential output impedance D Z Single-ended output impedance SE Z Single-ended output impedance matching MSE J Deterministic jitter D J Total jitter T Table 16 89TSF500 SerDes Interface Transmitter Characteristics (Part ...

Page 13

IDT 89TSF500 Register Field 1 Value Table 19 SERDES Tx Typical Pre-Emphasis Levels for Tx Amplitude Setting 3 (1200mV typical) 1. Differential voltage values are configurable via settings in the SerDes Group ...

Page 14

IDT 89TSF500 Z0 = 50Ω For output timing 89TSF500 Thermal Considerations This section describes the temperature and heat sink calculations for flip-chip BGA devices. Symbol Ø Thermal resistance, junction to ambient (no heat sink) JA Ø Estimated thermal resistance, junction ...

Page 15

IDT 89TSF500 The following graph depicts the ambient temperature (T 80.0 70.0 60.0 50.0 40.0 30.0 For system designers, specification of the maximum device junction temperature (operating) is critical, since it allows them to select a heat sink that meets ...

Page 16

IDT 89TSF500 89TSF500 Power, Reset, and Initialization Sequencing Requirements Power Supply Power-Up Sequence There is a power supply power-up sequence requirement that addresses potential latchup issues with some I/O buffers. All 3.3V I/O power must ramp up before all other ...

Page 17

IDT 89TSF500 Device Reset It is possible to reset the entire 89TSF500 except for the PLL. To reset the device without being required to re-initialize the PLL, assert the RESET_N pin (low) for at least 16 clocks (SYS_CLK) and then ...

Page 18

IDT 89TSF500 89TSF500 Pin List Pin Signal I/O A2 DNC DNC A3 DNC DNC A4 VDD_IO P A5 DNC DNC A6 VSS P A7 DNC DNC A8 VDD_IO P A9 DNC DNC A10 TDI I A11 TCK I A12 VSS ...

Page 19

IDT 89TSF500 Pin Signal I/O C10 RPU I C11 TMS I C12 VSS P C13 DNC DNC C14 VSS P C15 TXN[31] O C16 TXP[31] O C17 TXN[30] O C18 TXP[30] O C19 TXN[29] O C20 TXP[29] O C21 TXN[28] ...

Page 20

IDT 89TSF500 Pin Signal I/O E18 DNC DNC E19 DNC DNC E20 DNC DNC E21 DNC DNC E22 DNC DNC E23 DNC DNC E24 DNC DNC E25 VSS P E26 DNC DNC E27 DNC DNC E28 DNC DNC E29 DNC ...

Page 21

IDT 89TSF500 Pin Signal I/O G26 DNC DNC G27 DNC DNC G28 DNC DNC G29 DNC DNC G30 DNC DNC G31 DNC DNC G32 DNC DNC G33 DNC DNC G34 DNC DNC G35 DNC DNC G36 VSS P G37 TXN[21] ...

Page 22

IDT 89TSF500 Pin Signal I/O J34 DNC DNC J35 DNC DNC J36 VSS P J37 TXN[20] O J38 VSS P J39 RXN[20 VSS P K2 DNC DNC K3 DNC DNC K4 VDD_IO P K5 DNC DNC K6 DNC ...

Page 23

IDT 89TSF500 Pin Signal I/O M3 DNC DNC M4 VSS P M5 DNC DNC M6 DNC DNC M7 DNC DNC M8 DNC DNC M9 DNC DNC M10 VSS P M11 VSS P M12 VDD_IO P M13 VDD_IO P M14 VDD_IO ...

Page 24

IDT 89TSF500 Pin Signal I/O P11 VSS P P12 VDD_IO P P13 VDD P P14 VSS P P15 VSS P P16 VSS P P17 VSS P P18 VSS P P19 VSS P P20 VSS P P21 VSS P P22 VSS ...

Page 25

IDT 89TSF500 Pin Signal I/O T19 VDD P T20 VDD P T21 VDD P T22 VDD P T23 VDD P T24 VDD P T25 VSS P T26 VSS P T27 VDD_SD P T28 VDD_TX P T29 VSS P T30 VSS ...

Page 26

IDT 89TSF500 Pin Signal I/O V27 VDD_SD P V28 VDD_TX P V29 VSS P V30 VSS P V31 DNC DNC V32 DNC DNC V33 DNC DNC V34 DNC DNC V35 DNC DNC V36 VSS P V37 TXP[16] O V38 VSS ...

Page 27

IDT 89TSF500 Pin Signal I/O Y35 DNC DNC Y36 DNC DNC Y37 DNC DNC Y38 VSS P Y39 SD1_REFCLKN I AA1 SYS_CLK I AA2 VSS P AA3 PLL_CORE_LCK O AA4 RPU I AA5 DNC DNC AA6 PLL_CORE_VSS P AA7 DNC ...

Page 28

IDT 89TSF500 Pin Signal I/O AC4 RPD I AC5 DNC DNC AC6 DNC DNC AC7 DNC DNC AC8 DNC DNC AC9 DNC DNC AC10 VSS P AC11 VSS P AC12 VDD_IO P AC13 VDD P AC14 VSS P AC15 VSS ...

Page 29

IDT 89TSF500 Pin Signal I/O AE12 VDD_IO P AE13 VDD P AE14 VSS P AE15 VSS P AE16 VSS P AE17 VSS P AE18 VSS P AE19 VSS P AE20 VSS P AE21 VSS P AE22 VSS P AE23 VSS ...

Page 30

IDT 89TSF500 Pin Signal I/O AG20 VDD_SD P AG21 VDD_SD P AG22 VDD_SD P AG23 VDD_SD P AG24 VDD_SD P AG25 VDD_SD P AG26 VDD_SD P AG27 VDD_SD P AG28 VDD_TX P AG29 VSS P AG30 VSS P AG31 DNC ...

Page 31

IDT 89TSF500 Pin Signal I/O AJ28 VSS P AJ29 VSS P AJ30 VSS P AJ31 DNC DNC AJ32 DNC DNC AJ33 DNC DNC AJ34 DNC DNC AJ35 DNC DNC AJ36 VSS P AJ37 TXN[12] O AJ38 VSS P AJ39 RXN[12] ...

Page 32

IDT 89TSF500 Pin Signal I/O AL36 VSS P AL37 TXN[11] O AL38 VSS P AL39 RXN[11] I AM1 DNC DNC AM2 DNC DNC AM3 DNC DNC AM4 DNC DNC AM5 DNC DNC AM6 DNC DNC AM7 DNC DNC AM8 DNC ...

Page 33

IDT 89TSF500 Pin Signal I/O AP5 DNC DNC AP6 DNC DNC AP7 DNC DNC AP8 DNC DNC AP9 DNC DNC AP10 DNC DNC AP11 DNC DNC AP12 DNC DNC AP13 DNC DNC AP14 DNC DNC AP15 DNC DNC AP16 DNC ...

Page 34

IDT 89TSF500 Pin Signal I/O AT13 DNC DNC AT14 VSS P AT15 VSS P AT16 VSS P AT17 VSS P AT18 VSS P AT19 VSS P AT20 VSS P AT21 VSS P AT22 VSS P AT23 VSS P AT24 SD0_REF_RES ...

Page 35

IDT 89TSF500 Pin Signal I/O AV21 VSS P AV22 VSS P AV23 VSS P AV24 VSS P AV25 VSS P AV26 VSS P AV27 VSS P AV28 VSS P AV29 VSS P AV30 VSS P AV31 VSS P AV32 VSS ...

Page 36

IDT 89TSF500 89TSF500 Package Diagram The 89TSF500 package is an Amkor FCBGA, having 1517 pins, with 1 mm pitch; a 39x39 pin array; and a 40x40 mm enclosure. The package geometry is shown below *Notice: The information ...

Page 37

IDT 89TSF500 Ordering Information Product Operating Device Family Voltage Family Valid Combinations 89TSF500BL Revision History November 23, 2004: Initial publication by IDT. CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054 5xx AA Package Product Detail 1517-pin ...

Related keywords