IDT89TTM552BL IDT, Integrated Device Technology Inc, IDT89TTM552BL Datasheet - Page 4

• Manufacturer Part Number: IDT89TTM552BL
• Description: IC TRAFFIC MANAGER 1192-FCBGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT89TTM552BL

• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 89TTM552BL

89TTSF500 Pin Description
IDT 89TSF500
In this data sheet, direction is indicated as follows: I for In, O for Out, B for Bidirectional, and P for power.
SYS_CLK (pin AA1)
PLL_CORE_LCK (pin AA3)
PLL_SYS_LCK (pin W3)
PLL_DIV_RST_N (pin U2)
PLL_RST (pin AB3)
PLL_CORE_VDDA (pin AB8)
PLL_CORE_VSSA (pin AA8)
PLL_CORE_VDD (pin AB6)
PLL_CORE_VSS (pin AA6)
PLL_SYS_VDDA (pin V6)
PLL_SYS_VSSA (pin W6)
PLL_SYS_VDD (pin V8)
PLL_SYS_VSS (pin W8)
Note: Information in this section is subject to change. Contact your IDT FAE before making design decisions.
SD[2:0]_REFCLKN
(pins A24, Y39, AW25)
SD[2:0]_REFCLKP
(pins A25, AA39, AW24)
SD[2:0]_REF_RES
(pins D25, AA36, AT24)
VDD_SD[2:0]_PLL
(pins J23, Y31, AL23)
VSS_SD[2:0]_PLL
(pins K22, W30, AK24)
VDD_REFCLK[2:0]
(pins J24, AA31, AL22)
Signal Name
Signal Name
Serdes diff input
Serdes diff input
I/O Type
Serdes Bidi
I/O Type
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
*Notice: The information in this document is subject to change without notice
1.8V AVDD
1.8V AVDD
3.3V AVDD
1.8V AVDD
VAA18
VAA33
VSS
AVSS
AVSS
VSS
VSS
Table 1 89TSF500 PLL Control and Power Pins
Table 2 89TSF500 SerDes Pins (Part 1 of 2)
Dir.
Dir.
O
P
P
P
I
I
O
O
P
P
P
P
P
P
P
P
I
I
I
4 of 37
250MHz
250MHz
Freq.
125 MHz
Freq.
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Reference clocks for both Rx and Tx.
The reference clock (SD[n]_REFCLKN and SD[n]_REFCLKP)
must be synchronous to twice the system clock (SYS_CLK)
input.
If an entire SerDes group is not used, the reference clock pins
for that group should be pulled down to VSS using a 300Ω to
1kΩ resistor.
Reference resistor pins used to generate bias currents for
both Rx and Tx.
To ensure proper biasing, connect each of these to VSS
through a 3.09 kΩ 1% resistor.
If an entire SerDes group is not used, the reference resistor
pins for that group should be connected to VDD_SD (1.8V).
SerDes common VDD = 1.8V. These are PLL analog power
pins and must be well filtered.
SerDes PLL ground
SerDes common VDD = 3.3V
33K Ω internal pullup
33K Ω internal pullup
Remarks
Remarks
Supply
Supply
Supply
Supply
Supply
Supply
Supply
Supply
N/A
N/A
N/A
November 23, 2004