IDT89TTM552BL IDT, Integrated Device Technology Inc, IDT89TTM552BL Datasheet - Page 11

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IDT89TTM552BL

Manufacturer Part Number
IDT89TTM552BL
Description
IC TRAFFIC MANAGER 1192-FCBGA
Manufacturer
IDT, Integrated Device Technology Inc
Datasheet

Specifications of IDT89TTM552BL

Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
89TTM552BL

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Company
Part Number
Manufacturer
Quantity
Price
Part Number:
IDT89TTM552BL
Manufacturer:
IDT
Quantity:
2
IDT 89TSF500
Symbol
(differential)
Symbol
Symbol
T
T
V
V
V
fo
RSDREFCI
V
D
FSDREFCI
Z
J
f
SDREF
V
DIFF1
DIFF2
DIFF3
SDREF
RTERM
RSense
T
t
SDREF
SDREF
LDR
V
J
J
I
drf
MAX
reye
roff
DR
TR
PP
Differential output (without pre-emphasis)
(amplitude setting 1)
Differential output (without pre-emphasis)
(amplitude setting 2)
Differential output (without pre-emphasis)
(amplitude setting 3)
Driver rise/fall time
Common mode range
“Eye” opening
SerDes reference clock frequency
Percentage duty cycle for SerDes reference clock
Random jitter for SerDes reference clock
Frequency offset between source and destination
SerDes reference clocks
SerDes reference clock input rise time (10% to
90%)
SerDes reference clock input fall time (90% to
10%)
Deterministic Jitter at receiver
Total jitter at receiver
Single-ended termination of differential inputs
Rx return loss
Rx common mode return loss
Input sensitivity
Maximum input voltage
“Eye” opening
Off current
Table 16 89TSF500 SerDes Interface Transmitter Characteristics (Part 1 of 2)
Parameter
Parameter
Parameter
Table 15 89TSF500 SerDes Interface Receiver Characteristics
*Notice: The information in this document is subject to change without notice
Table 14 89TSF500 SerDes Reference Clock Characteristics
11 of 37
Min
TBD
TBD
TBD
TBD
Min
–100
Min
TBD
TBD
300
200
140
-50
1.5
40
45
Typical
Typical
Typical
1100
1200
TBD
2 × f
625
400
2
SYS
1
Max
Max
Max
TBD
TBD
TBD
TBD
+100
2000
TBD
TBD
0.41
0.65
60
55
50
3
5
Units
Units
Units
mV
mV
mV
Ohm
MHz
ppm
ps
mV
mV
mV
mA
dB
dB
ps
ns
ns
UI
UI
ps
%
V
Common mode should
be VDD_REFCLK – 1/2
eye opening
The expected frequency
is 250 MHz
(2 ×125 MHz)
Maximum current into a
100 MHz to 1.875 GHz
100 MHz to 1.875 GHz
Differential peak-peak
Differential peak-peak
Measured at 20–80%
Refer to Table 17.
Refer to Table 18.
Refer to Table 19.
pin with power off
Conditions
at 10
Notes
Notes
November 23, 2004
T
T
RMS
RZBCI
FZBCI
-12
BER

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