TC58V64ADC-T051 Toshiba, TC58V64ADC-T051 Datasheet - Page 18

• Manufacturer Part Number: TC58V64ADC-T051
• Description: IC 64MBIT NAND SMART 3V 44TSOP
• Manufacturer: Toshiba

Specifications of TC58V64ADC-T051

• Memory Size: 8MB
• Memory Type: EEPROM - Smart Media
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: TC58V64DC-CT0501; TC58V64DC-CT0501

DEVICE OPERATION
Select page
Select page
RY
RY
CLE
CLE
ALE
ALE
Read Mode (1)
timing details and the block diagram.
Read Mode (2)
/
/
WE
WE
RE
RE
CE
BY
CE
BY
I/O
I/O
N
N
Read mode (1) is set when a 00H command is issued to the Command register. Refer to Figure 3 below for
00H
01H
M
Figure 3. Read mode (1) operation
Figure 4. Read mode (2) operation
M
M
Start-address input
Start-address input
256
N
N
M
527
527
Busy
Busy
Cell array
Cell array
starts on the rising edge of WE in the third cycle (after the
address information has been latched). The device will be in
Busy state during this transfer period. The CE signal must
stay Low after the third address input and during Busy state.
Serial data can be output synchronously with the RE clock
from the start pointer designated in the address input cycle.
the same as that of Read mode (1). If the start pointer is to be
set after column address 256, use Read mode (2).
starts from column address 0.
A data transfer operation from the cell array to the register
After the transfer period the device returns to Ready state.
The operation of the device after input of the 01H command is
However, for a Sequential Read, output of the next page
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TC58V64ADC