MT18HTF12872AY-53EB1 Micron Technology Inc, MT18HTF12872AY-53EB1 Datasheet
MT18HTF12872AY-53EB1
Specifications of MT18HTF12872AY-53EB1
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MT18HTF12872AY-53EB1 Summary of contents
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DR, ECC) 240-Pin DDR2 SDRAM UDIMM DDR2 SDRAM Unbuffered DIMM (UDIMM) MT18HTF6472A – 512MB MT18HTF12872A – 1GB MT18HTF25672A – 2GB MT18HTF51272A – 4GB For component data sheets, refer to Micron’s Web site: Features • 240-pin, ...
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... Table 4: Part Numbers and Timing Parameters – 1GB Modules Base device: MT47H64M8 Module 1 Part Number Density MT18HTF12872AY-80E__ MT18HTF12872AY-800__ MT18HTF12872AY-667__ MT18HTF12872AY-53E__ MT18HTF12872AY-40E__ Table 5: Part Numbers and Timing Parameters – 2GB Modules Base device: MT47H128M8 Module 1 Part Number Density MT18HTF25672AY-80E__ MT18HTF25672AY-800__ MT18HTF25672AY-667__ MT18HTF25672AY-53E__ ...
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... MT18HTF51272AY-53E__ MT18HTF51272AY-40E__ Notes: 1. All part numbers end with a two-place code (not shown) that designating component and PCB revisions. Consult factory for current revision codes. Example: MT18HTF12872AY- 667D4. 2. For component data sheets, refer to Micron’s Web PDF: 09005aef80e8ad4d/Source: 09005aef80e785e6 HTF18C64_128_256_512x72A.fm - Rev. H 5/08 EN ...
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DR, ECC) 240-Pin DDR2 SDRAM UDIMM Pin Assignments and Descriptions Table 7: Pin Assignments 240-Pin UDIMM Front Pin Symbol Pin Symbol Pin Symbol Pin Symbol DQ19 61 REF ...
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DR, ECC) 240-Pin DDR2 SDRAM UDIMM Table 8: Pin Descriptions Symbol Type ODT0, ODT1 Input On-die termination: ODT (registered HIGH) enables termination resistance internal to (SSTL_18) the DDR2 SDRAM. When enabled, ODT is only applied ...
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DR, ECC) 240-Pin DDR2 SDRAM UDIMM Functional Block Diagram Figure 2: Functional Block Diagram S1# S0 DQS0 DQS0 DM0 DM DQ0 DQ DQ1 DQ DQ2 DQ DQ3 DQ DQ4 DQ DQ5 ...
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... READs and by the memory controller during WRITEs. DQS is edge- aligned with data for READs and center-aligned with data for WRITEs. DDR2 SDRAM modules operate from a differential clock (CK and CK#); the crossing of CK going HIGH and CK# going LOW will be referred to as the positive edge of CK. ...
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... Simulations are significantly more accurate and realistic than a gross estimation of module capacitance when inductance and delay parameters associated with trace lengths are used in simulations. JEDEC modules are currently designed using simulations to close timing budgets. Component AC Timing and Operating Conditions Recommended AC operating conditions are given in the DDR2 component data sheets. Component specifications are available on Micron’ ...
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DR, ECC) 240-Pin DDR2 SDRAM UDIMM I Specifications DD Table 11: DDR2 I Specifications and Conditions – 512MB DD Values shown for MT47H32M8 DDR2 SDRAM only and are computed from values specified in the 256Mb ...
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DR, ECC) 240-Pin DDR2 SDRAM UDIMM Table 12: DDR2 I Specifications and Conditions – 1GB DD Values shown for MT47H64M8 DDR2 SDRAM only and are computed from values specified in the 512Mb (64 Meg x ...
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DR, ECC) 240-Pin DDR2 SDRAM UDIMM Table 13: DDR2 I Specifications and Conditions (Die Revision A) – 2GB DD Values shown for MT47H128M8 DDR2 SDRAM only and are computed from values specified in the 1Gb ...
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DR, ECC) 240-Pin DDR2 SDRAM UDIMM Table 14: DDR2 I Specifications and Conditions (Die Revision E) – 2GB DD Values shown for MT47H128M8 DDR2 SDRAM only and are computed from values specified in the 1Gb ...
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DR, ECC) 240-Pin DDR2 SDRAM UDIMM Table 15: DDR2 I Specifications and Conditions – 4GB DD Values shown for MT47H256M8 DDR2 SDRAM only and are computed from values specified in the 2Gb (256 Meg x ...
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DR, ECC) 240-Pin DDR2 SDRAM UDIMM Serial Presence-Detect Table 16: Serial Presence-Detect EEPROM DC Operating Conditions All voltages referenced to V Parameter/Condition Supply voltage Input high voltage: Logic 1; All inputs Input low voltage: Logic ...
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DR, ECC) 240-Pin DDR2 SDRAM UDIMM Table 18: Serial Presence-Detect Matrix Byte Description 0 Number of SPD bytes used by Micron 1 Total number of bytes in SPD device 2 Fundamental memory type 3 Number ...
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DR, ECC) 240-Pin DDR2 SDRAM UDIMM Table 18: Serial Presence-Detect Matrix (continued) Byte Description 27 MIN row precharge time, 28 MIN row active-to-row active, 29 MIN RAS#-to-CAS# delay, 30 MIN active-to-precharge time, 31 Module rank ...
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DR, ECC) 240-Pin DDR2 SDRAM UDIMM Table 18: Serial Presence-Detect Matrix (continued) Byte Description 47–61 Optional features, not supported 62 SPD revision 63 Checksum for bytes 0–62 64 Manufacturer’s JEDEC ID code 65–71 Manufacturer’s JEDEC ...
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DR, ECC) 240-Pin DDR2 SDRAM UDIMM Module Dimensions Figure 3: 240-Pin DDR2 DIMM 2.00 (0.079) R (4X 2.50 (0.098) D (2X) 2.30 (0.091) TYP PIN 1 2.20 (0.087) TYP 1.0 (0.039) TYP 1.0 ...