MT18HTF12872AY-53EB1 Micron Technology Inc, MT18HTF12872AY-53EB1 Datasheet - Page 14
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MT18HTF12872AY-53EB1
Manufacturer Part Number
MT18HTF12872AY-53EB1
Description
MODULE SDRAM DDR2 1GB 240DIMM
Manufacturer
Micron Technology Inc
Datasheet
1.MT18HTF12872AY-53EB1.pdf
(18 pages)
Specifications of MT18HTF12872AY-53EB1
Memory Type
DDR2 SDRAM
Memory Size
1GB
Speed
533MT/s
Package / Case
240-DIMM
Main Category
DRAM Module
Sub-category
DDR2 SDRAM
Module Type
240UDIMM
Device Core Size
72b
Organization
128Mx72
Total Density
1GByte
Chip Density
512Mb
Access Time (max)
50ps
Maximum Clock Rate
533MHz
Operating Supply Voltage (typ)
1.8V
Operating Current
1.368A
Number Of Elements
18
Operating Supply Voltage (max)
1.9V
Operating Supply Voltage (min)
1.7V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Pin Count
240
Mounting
Socket
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Serial Presence-Detect
Table 16:
Table 17:
PDF: 09005aef80e8ad4d/Source: 09005aef80e785e6
HTF18C64_128_256_512x72A.fm - Rev. H 5/08 EN
Parameter/Condition
Parameter/Condition
Supply voltage
Input high voltage: Logic 1; All inputs
Input low voltage: Logic 0; All inputs
Output low voltage: I
Input leakage current: V
Output leakage current: V
Standby current
Power supply current, READ: SCL clock frequency = 100 KHz
Power supply current, WRITE: SCL clock frequency = 100 KHz
SCL LOW to SDA data-out valid
Time the bus must be free before a new transition can start
Data-out hold time
SDA and SCL fall time
Data-in hold time
Start condition hold time
Clock HIGH period
Noise suppression time constant at SCL, SDA inputs
Clock LOW period
SDA and SCL rise time
SCL clock frequency
Data-in setup time
Start condition setup time
Stop condition setup time
WRITE cycle time
Serial Presence-Detect EEPROM DC Operating Conditions
All voltages referenced to V
Serial Presence-Detect EEPROM AC Operating Conditions
All voltages referenced to V
Notes:
OUT
IN
= 3mA
OUT
= GND to V
1. To avoid spurious start and stop conditions, a minimum delay is placed between SCL = 1 and
2. This parameter is sampled.
3. For a restart condition or following a WRITE cycle.
4. The SPD EEPROM WRITE cycle time (
512MB, 1GB, 2GB, 4GB (x72, DR, ECC) 240-Pin DDR2 SDRAM UDIMM
= GND to V
the falling or rising edge of SDA.
sequence to the end of the EEPROM internal ERASE/PROGRAM cycle. During the WRITE
cycle, the EEPROM bus interface circuit is disabled, SDA remains HIGH due to the pull-up
resistor, and the EEPROM does not respond to its slave address.
DD
SS
SS
DD
; V
; V
DDSPD
DDSPD
= +1.7V to +3.6V
= +1.7V to +3.6V
14
Symbol
t
t
t
t
t
HD:DAT
HD:STA
SU:DAT
t
SU:STO
SU:STA
t
t
WRC) is the time from a valid STOP condition of a write
Symbol
t
t
HIGH
LOW
V
f
WRC
t
t
BUF
SCL
AA
DH
t
t
I
DDSPD
t
I
Micron Technology, Inc., reserves the right to change products or specifications without notice.
V
R
CC W
F
V
V
I
I
I
CC R
I
LO
SB
OL
LI
IH
IL
V
Min
200
100
0.2
1.3
0.6
0.6
1.3
0.6
0.6
DDSPD
0
–
–
–
–
–
Min
0.10
0.05
–0.6
1.7
1.6
0.4
2
–
× 0.7
Serial Presence-Detect
Max
300
400
0.9
0.3
50
10
–
–
–
–
–
–
–
–
–
©2003 Micron Technology, Inc. All rights reserved.
V
V
DDSPD
DDSPD
Max
3.6
0.4
3
3
4
1
3
Units
+ 0.5
× 0.3
KHz
ms
µs
µs
ns
ns
µs
µs
µs
ns
µs
µs
ns
µs
µs
Units
Notes
mA
mA
µA
µA
µA
V
V
V
V
1
2
2
3
4