MT18LSDT12872AG-133C1 Micron Technology Inc, MT18LSDT12872AG-133C1 Datasheet - Page 12
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MT18LSDT12872AG-133C1
Manufacturer Part Number
MT18LSDT12872AG-133C1
Description
MODULE SDRAM 1GB 168DIMM
Manufacturer
Micron Technology Inc
Datasheet
1.MT18LSDT12872AG-133C1.pdf
(29 pages)
Specifications of MT18LSDT12872AG-133C1
Memory Type
SDRAM
Memory Size
1GB
Speed
133MHz
Package / Case
168-DIMM
Main Category
DRAM Module
Sub-category
SDRAM
Module Type
168UDIMM
Device Core Size
72b
Organization
128Mx72
Total Density
1GByte
Chip Density
512Mb
Access Time (max)
6/5.4ns
Maximum Clock Rate
133MHz
Operating Supply Voltage (typ)
3.3V
Operating Current
1.157A
Number Of Elements
18
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
3V
Operating Temp Range
0C to 65C
Operating Temperature Classification
Commercial
Pin Count
168
Mounting
Socket
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Figure 6:
CAS Latency
Operating Mode
PDF: 09005aef8088b1bf/Source: 09005aef808807ca
SD9_18C64_128X72AG.fm - Rev. C 6/05 EN
CAS Latency Diagram
COMMAND
COMMAND
The CAS latency is the delay, in clock cycles, between the registration of a READ com-
mand and the availability of the first piece of output data. The latency can be set to two
or three clocks.
If a READ command is registered at clock edge n, and the latency is m clocks, the data
will be available by clock edge n + m. The DQs will start driving as a result of the clock
edge one cycle earlier (n + m - 1), and provided that the relevant access times are met,
the data will be valid by clock edge n + m. For example, assuming that the clock cycle
time is such that all relevant access times are met, if a READ command is registered at T0
and the latency is programmed to two clocks, the DQs will start driving after T1 and the
data will be valid by T2, as shown in Figure 6. Table 7 on page 13, indicates the operating
frequencies at which each CAS latency setting can be used.
Reserved states should not be used as unknown operation or incompatibility with future
versions may result.
The normal operating mode is selected by setting M7 and M8 to zero; the other combi-
nations of values for M7 and M8 are reserved for future use and/or test modes. The pro-
grammed burst length applies to both READ and WRITE bursts.
Test modes and reserved states should not be used because unknown operation or
incompatibility with future versions may result.
CLK
CLK
DQ
DQ
512MB (SR), 1GB (DR): (x72, ECC) 168-Pin SDRAM UDIMM
READ
READ
T0
T0
CAS latency = 2
NOP
NOP
T1
T1
12
t
t AC
LZ
CAS latency = 3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
T2
NOP
T2
NOP
t
t AC
D
LZ
t OH
OUT
Mode Register Definition
T3
T3
NOP
D
t OH
OUT
DON’T CARE
UNDEFINED
©2002 Micron Technology, Inc. All rights reserved.
T4