MT18LSDT12872AG-133C1 Micron Technology Inc, MT18LSDT12872AG-133C1 Datasheet - Page 25
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MT18LSDT12872AG-133C1
Manufacturer Part Number
MT18LSDT12872AG-133C1
Description
MODULE SDRAM 1GB 168DIMM
Manufacturer
Micron Technology Inc
Datasheet
1.MT18LSDT12872AG-133C1.pdf
(29 pages)
Specifications of MT18LSDT12872AG-133C1
Memory Type
SDRAM
Memory Size
1GB
Speed
133MHz
Package / Case
168-DIMM
Main Category
DRAM Module
Sub-category
SDRAM
Module Type
168UDIMM
Device Core Size
72b
Organization
128Mx72
Total Density
1GByte
Chip Density
512Mb
Access Time (max)
6/5.4ns
Maximum Clock Rate
133MHz
Operating Supply Voltage (typ)
3.3V
Operating Current
1.157A
Number Of Elements
18
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
3V
Operating Temp Range
0C to 65C
Operating Temperature Classification
Commercial
Pin Count
168
Mounting
Socket
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Table 22:
PDF: 09005aef8088b1bf/Source: 09005aef808807ca
SD9_18C64_128X72AG.fm - Rev. C 6/05 EN
Byte
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
0
1
2
3
4
5
6
7
8
9
Description
Number of bytes used by Micron
Total number of SPD memory bytes
Memory type
Number of row addresses
Number of column addresses
Number of module ranks
Module data width
Module data width (continued)
Module voltage interface levels
SDRAM cycle time,
(CAS latency = 3)
SDRAM access from CLK,
(CAS latency = 3)
Module configuration type
Refresh rate/type
SDRAM width (primary SDRAM)
Error-checking SDRAM data width
Minimum clock delay from back-to-back random
column addresses,
Burst lengths supported
Number of banks on SDRAM device
CAS latencies supported
CS latency
WE latency
SDRAM module attributes
SDRAM device attributes: General
SDRAM cycle time,
(CAS latency = 2)
SDRAM access from CLK,
(CAS latency = 2)
SDRAM cycle time,
SDRAM access from CLK,
Minimum row precharge time,
Minimum row active to row active,
Minimum RAS# to CAS# delay,
Minimum RAS# pulse width,
(see note 1)
Module rank density
Command and address setup time,
Command and address hold time,
Data signal input setup time,
Data signal input hold time,
Serial Presence-Detect Matrix
V
DD
= +3.3V ±0.3V; “1”/”0”: Serial Data, “driven to HIGH”/”driven to LOW”
t
CCD
t
t
t
CK
CK
CK (CAS latency = 1)
t
t
t
AC
AC
AC (CAS latency = 1)
t
t
DH
RAS
t
DS
t
t
RCD
RP
512MB (SR), 1GB (DR): (x72, ECC) 168-Pin SDRAM UDIMM
t
AH,
t
t
AS,
RRD
t
t
CMH
CMS
25
5.4ns (-13E/-133)
1.5ns (-13E/-133)
0.8ns (-13E/-133)
1.5ns (-13E/-133)
0.8ns (-13E/-133)
1, 2, 4, 8, PAGE
7.8125µs/SELF
UNBUFFERED
7.5ns (-133)
5.4ns (-13E)
10ns (-133)
15ns (-13E)
20ns (-133)
14ns (-13E)
15ns (-133)
15ns (-13E)
20ns (-133)
45ns (-13E)
7.5ns (13E)
(Version)
44ns (133)
7ns (-13E)
6ns (-133)
SDRAM
512MB
Entry
1 or 2
LVTTL
ECC
128
256
2, 3
13
11
72
0E
0
8
8
1
4
0
0
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT9LSDT6472A
0D
A0
2D
0B
2C
80
08
04
01
48
00
01
70
75
54
02
82
08
08
01
8F
04
06
01
01
00
0E
75
54
60
00
00
0F
14
0E
0F
0F
14
80
15
08
15
08
Serial Presence Detect
©2002 Micron Technology, Inc. All rights reserved.
MT18LSDT12872A
0D
0B
A0
2D
2C
80
08
04
02
48
00
01
75
75
54
02
82
08
08
01
8F
04
06
01
01
00
0E
75
54
60
00
00
0F
14
0E
0F
0F
14
80
15
08
15
08