MT18LSDT12872AG-133C1 Micron Technology Inc, MT18LSDT12872AG-133C1 Datasheet - Page 22
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MT18LSDT12872AG-133C1
Manufacturer Part Number
MT18LSDT12872AG-133C1
Description
MODULE SDRAM 1GB 168DIMM
Manufacturer
Micron Technology Inc
Datasheet
1.MT18LSDT12872AG-133C1.pdf
(29 pages)
Specifications of MT18LSDT12872AG-133C1
Memory Type
SDRAM
Memory Size
1GB
Speed
133MHz
Package / Case
168-DIMM
Main Category
DRAM Module
Sub-category
SDRAM
Module Type
168UDIMM
Device Core Size
72b
Organization
128Mx72
Total Density
1GByte
Chip Density
512Mb
Access Time (max)
6/5.4ns
Maximum Clock Rate
133MHz
Operating Supply Voltage (typ)
3.3V
Operating Current
1.157A
Number Of Elements
18
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
3V
Operating Temp Range
0C to 65C
Operating Temperature Classification
Commercial
Pin Count
168
Mounting
Socket
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Figure 8:
Figure 9:
Table 18:
Table 19:
PDF: 09005aef8088b1bf/Source: 09005aef808807ca
SD9_18C64_128X72AG.fm - Rev. C 6/05 EN
Mode
Memory area select code (two arrays)
Protection register select code
Current address read
Random address read
Sequential read
Byte write
Page write
SCL from Master
Data Output
from Transmitter
Data Output
from Receiver
EEPROM Device Select Code
The most significant bit (b7) is sent first
EEPROM Operating Modes
Definition of Start and Stop
Acknowledge Response From Receiver
SDA
SCL
RW Bit
1
0
1
1
0
0
Start
bit
512MB (SR), 1GB (DR): (x72, ECC) 168-Pin SDRAM UDIMM
V
V
V
V
IH
IH
IH
IH
WC
V
V
or V
or V
or V
or V
IL
IL
IL
IL
IL
IL
b7
1
0
Device Type Identifier
22
Bytes
≤ 16
≥ 1
1
1
1
b6
0
1
Start, device select, RW = 1
Start, device select, RW= 0, Address
Restart, device select, RW= 1
Similar to current or random address read
Start, device select, RW = 0
Start, device select, RW = 0
Micron Technology, Inc., reserves the right to change products or specifications without notice.
b5
1
1
Stop
bit
b4
0
0
8
Initial Sequence
SA2
SA2
b3
Serial Presence Detect
Chip Enable
©2002 Micron Technology, Inc. All rights reserved.
Acknowledge
SA1
SA1
b2
9
SA0
SA0
b1
RW
RW
RW
b0