MT18LSDT12872AG-133C1 Micron Technology Inc, MT18LSDT12872AG-133C1 Datasheet - Page 21

• Manufacturer Part Number: MT18LSDT12872AG-133C1
• Description: MODULE SDRAM 1GB 168DIMM
• Manufacturer: Micron Technology Inc

Specifications of MT18LSDT12872AG-133C1

• Memory Type: SDRAM
• Memory Size: 1GB
• Speed: 133MHz
• Package / Case: 168-DIMM
• Main Category: DRAM Module
• Sub-category: SDRAM
• Module Type: 168UDIMM
• Device Core Size: 72b
• Organization: 128Mx72
• Total Density: 1GByte
• Chip Density: 512Mb
• Access Time (max): 6/5.4ns
• Maximum Clock Rate: 133MHz
• Operating Supply Voltage (typ): 3.3V
• Operating Current: 1.157A
• Number Of Elements: 18
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Operating Temp Range: 0C to 65C
• Operating Temperature Classification: Commercial
• Pin Count: 168
• Mounting: Socket
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Serial Presence Detect
SPD Clock and Data Conventions
SPD Start Condition
SPD Stop Condition
SPD Acknowledge
Figure 7:
PDF: 09005aef8088b1bf/Source: 09005aef808807ca
SD9_18C64_128X72AG.fm - Rev. C 6/05 EN
Data Validity
Data states on the SDA line can change only during SCL LOW. SDA state changes during
SCL HIGH are reserved for indicating start and stop conditions (as shown in Figure 7,
and Figure 8 on page 22).
All commands are preceded by the start condition, which is a HIGH-to-LOW transition
of SDA when SCL is HIGH. The SPD device continuously monitors the SDA and SCL
lines for the start condition and will not respond to any command until this condition
has been met.
All communications are terminated by a stop condition, which is a LOW-to-HIGH tran-
sition of SDA when SCL is HIGH. The stop condition is also used to place the SPD device
into standby power mode.
Acknowledge is a software convention used to indicate successful data transfers. The
transmitting device, either master or slave, will release the bus after transmitting 8 bits.
During the ninth clock cycle, the receiver will pull the SDA line LOW to acknowledge that
it received the 8 bits of data (as shown in Figure 9 on page 22).
The SPD device will always respond with an acknowledge after recognition of a start
condition and its slave address. If both the device and a WRITE operation have been
selected, the SPD device will respond with an acknowledge after the receipt of each sub-
sequent 8-bit word. In the read mode, the SPD device will transmit 8 bits of data, release
the SDA line, and monitor the line for an acknowledge. If an acknowledge is detected
and no stop condition is generated by the master, the slave will continue to transmit
data. If an acknowledge is not detected, the slave will terminate further data transmis-
sions and await the stop condition to return to standby power mode.
SDA
SCL
512MB (SR), 1GB (DR): (x72, ECC) 168-Pin SDRAM UDIMM
Data stable
change
Data
21
Data stable
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Serial Presence Detect
©2002 Micron Technology, Inc. All rights reserved.