MT9VDDT6472PHG-335F2 Micron Technology Inc, MT9VDDT6472PHG-335F2 Datasheet - Page 17
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MT9VDDT6472PHG-335F2
Manufacturer Part Number
MT9VDDT6472PHG-335F2
Description
MODULE DDR SDRAM 512MB 200SODIMM
Manufacturer
Micron Technology Inc
Datasheet
1.MT9VDDT1672PHG-335D2.pdf
(33 pages)
Specifications of MT9VDDT6472PHG-335F2
Memory Type
DDR SDRAM
Memory Size
512MB
Speed
333MT/s
Package / Case
200-SODIMM
Main Category
DRAM Module
Sub-category
DDR SDRAM
Module Type
200SODIMM
Device Core Size
72b
Organization
64Mx72
Total Density
512MByte
Chip Density
512Mb
Access Time (max)
700ps
Maximum Clock Rate
333MHz
Operating Supply Voltage (typ)
2.5V
Operating Current
1.4A
Number Of Elements
9
Operating Supply Voltage (max)
2.7V
Operating Supply Voltage (min)
2.3V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Pin Count
200
Mounting
Socket
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MT9VDDT6472PHG-335F2
Manufacturer:
MICRON
Quantity:
1 001
Table 16: Capacitance)
Note: 11; notes appear on pages 19–22
Table 17: Electrical Characteristics and Recommended AC Operating Conditions
DDR SDRAM components only; notes appear on pages 19–22
Notes: 1–5, 12–15, 29, 47; 0°C
pdf: 09005aef808ffe58, source: 09005aef808ffdc7
DD9C16_32_64_128x72PHG.fm - Rev. B 9/04 EN
PARAMETER
Access window of DQs from CK/CK#
CK high-level width
CK low-level width
Clock cycle time
DQ and DM input hold time relative to
DQS
DQ and DM input setup time relative to
DQS
DQ and DM input pulse width (for each
input)
Access window of DQS from CK/CK#
DQS input high pulse width
DQS input low pulse width
DQS-DQ skew, DQS to last DQ valid, per
group, per access
Write command to first DQS latching
transition
DQS falling edge to CK rising - setup time
DQS falling edge from CK rising - hold
time
Half clock period
Data-out high-impedance window from
CK/CK#
Data-out low-impedance window from
CK/CK#
Address and control input hold time
(slow slew rate)
Address and control input setup time
(slow slew rate)
Address and Control input pulse width
(for each input)
LOAD MODE REGISTER command cycle
time
PARAMETER
Input/Output Capacitance: DQ, DQS, DM
Input Capacitance: Command and Address, S#, CKE
Input Capacitance: CK, CK#
AC CHARACTERISTICS
CL = 2.5
CL = 2
T
A
+70°C; V
128MB, 256MB, 512MB, 1GB (x72, ECC, PLL, SR)
SYMBOL
t
t
CK (2.5)
t
t
DD
DQSCK
t
t
t
t
t
CK (2)
DQSH
DQSQ
DIPW
DQSL
DQSS
t
t
t
MRD
t
t
t
t
t
DSH
t
t
IPW
t
DSS
t
t
DH
AC
CH
IH
DS
HP
HZ
IS
CL
LZ
= V
S
S
DD
Q = +2.5V ±0.2V
-0.60
-0.70
MIN
0.45
0.45
0.45
0.45
1.75
0.35
0.35
0.75
0.75
0.75
0.80
-0.7
7.5
0.2
0.2
2.2
6
t
CH,
-335
17
t
CL
+0.60
+0.70
MAX
+0.7
0.55
0.55
0.45
1.25
13
13
SYMBOL
200-PIN DDR SDRAM SODIMM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
C
C
C
IO
I 1
I 2
-0.75
-0.75
-0.75
MIN
0.90
0.90
0.45
0.45
1.75
0.35
0.35
0.75
7.5
7.5
0.5
0.5
0.2
0.2
2.2
15
t
CH,
-262
t
CL
MAX
+0.75
+0.75
+0.75
0.55
0.55
1.25
0.5
13
13
MIN
18.0
4.0
-
-0.75
-0.75
-0.75
MIN
0.45
0.45
1.75
0.35
0.35
0.75
7.5
0.5
0.5
0.2
0.2
1.1
1.1
2.2
10
15
-26A/-265
t
©2004 Micron Technology, Inc. All rights reserved.
CH,
TYP
7.7
-
-
t
CL
MAX
+0.75
+0.75
+0.75
0.55
0.55
1.25
0.6
13
13
MAX
27.0
5.0
-
UNITS NOTES
ADVANCE
t
t
t
t
t
t
t
ns
CK
CK
ns
ns
ns
ns
ns
ns
CK
CK
ns
CK
CK
CK
ns
ns
ns
ns
ns
ns
ns
UNITS
pF
pF
pF
40, 45
40, 45
23, 27
23, 27
22, 23
16, 37
16, 37
26
26
27
30
12
12